Displaying 6 results from an estimated 6 matches for "cpu64reg".
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cpu64regs
2013 Mar 25
0
[LLVMdev] [PATCH] RegScavenger::scavengeRegister
...cult problem to solve. Is that right?
That depends.
The register allocator can spill across register classes, but it calls the functionality "live range splitting" and "register class inflation". Here's how you enable it:
- Define a union register class that contains both CPU64Regs and ACRegs.
- Implement TRI::getLargestLegalSuperClass(), and return the new union register class when asked about CPU64Regs or ACRegs (or their sub-classes).
- Teach TII::copyPhysReg() to handle the cross-class copies.
- Teach TII::storeRegToStackSlot() to constrain the register class to CPU64...
2013 Mar 25
3
[LLVMdev] [PATCH] RegScavenger::scavengeRegister
Hi Jakob,
I believe Hal is trying to enable register scavenger to find two (or more)
registers that can be used as temporaries.
One problem I see with this approach is that, if you use register scavenger
during PEI, you will have to pessimistically set aside two emergency spill
slots before you call scavengeRegister, even if it turns out you only need
one. Having an extra stack slot might not be
2013 Mar 25
2
[LLVMdev] [PATCH] RegScavenger::scavengeRegister
...>
> That depends.
>
> The register allocator can spill across register classes, but it calls the
> functionality "live range splitting" and "register class inflation". Here's
> how you enable it:
>
> - Define a union register class that contains both CPU64Regs and ACRegs.
>
> - Implement TRI::getLargestLegalSuperClass(), and return the new union
> register class when asked about CPU64Regs or ACRegs (or their sub-classes).
>
> - Teach TII::copyPhysReg() to handle the cross-class copies.
>
> - Teach TII::storeRegToStackSlot() to const...
2012 Oct 06
2
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...to another file):
def SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>,
SDTCisVT<1, f64>]>;
def MipsCopyF64 : SDNode<"MIPSISD::CopyF64",
SDT_MIPSCopyF64>;
I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired register class)
in the DMFC1 rule for testing.
Next, I added the code in ExpandPseudo to use the following pseudo
instruction expansion:
void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB,
MachineBas...
2012 Oct 09
0
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>,
> SDTCisVT<1, f64>]>;
>
> def MipsCopyF64 : SDNode<"MIPSISD::CopyF64",
> SDT_MIPSCopyF64>;
>
> I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired register class)
> in the DMFC1 rule for testing.
>
> Next, I added the code in ExpandPseudo to use the following pseudo
> instruction expansion:
>
> void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB,
>...
2012 Aug 18
1
[LLVMdev] MIPS Register Pressure Limit.
Hello,
why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM.
Thanks in advance.
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