search for: cpu0instrinfo

Hi Johnny, Thank you for your help. I guess the pseudo instruction does not interfere in the generated assembly code. I'll check the file that describes the registers and I hope understand why the assembly code is printed wrong (now is printed things like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote:

...experience like me, it is really hard to extract the fundamental structure from existing backends, e.g., what is necessary for an early stage and what is the refined result after years of development. For example, everything went well with Cpu0RegisterInfo.td, with only a little struggle. But for Cpu0InstrInfo.td, questions start to come up: Why simm16 is inherited from Operand<i32>? What are PatLeaf and ComplexPattern? What is isReMaterializable? etc. Every line of description, every occurrence of new keyword or concept would confuse a beginner reader. They need to find enough information to follo...

I was wondering if this shouldn't somehow find its way into the official LLVM documentation? It certainly seems to qualify to become official documentation in my eyes. Nearly any LLVM backend writer out there should be able to benefit from reading about your experiences, I'd think. I know it is not as generic and abstract as what the LLVM dev list seems to prefer, but I personally find

Hi, I am writing an llvm backend tutorial through my learning process of llvm backend study and implementation. Web as follows, http://jonathan2251.github.com/lbd/index.html It include 10,000 lines of sources code for 1. Step by step, create an llvm backend for the Cpu0 which beginning from a CPU design for school teaching purpose in system programming. 2. ELF linker for Cpu0 which extended