search for: cpp0xmap

...ly return a clobber result in such cases. My next steps will probably be to improve the compilation of acquire atomics in the ARM backend. In particular, they are currently compiled by a load + dmb, while a load + dependant useless branch + isb is also valid (see http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html for example) and may be faster. Even better: if there is already a dependant branch (such as the loop for the lowering of CAS), it is just a cheap isb. The main step will be switching off the InsertFencesForAtomic flag, and do the lowering of atomics in the backend, because once an acquir...

...code This would more normally be done via target hooks in LLVM, though the principle is sound. > But it must be target-dependent as for example on Power a > seq_cst store has a fence before it, while on ARM it has a fence > both before and after it (per http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html) That certainly seems to suggest some kind of parametrisation. > For this exact reason, I am planning on splitting AtomicExpandLoadLinkedPass > in a target-independent and a target-dependent file: the current pass claims > to be target-independent but is actually designed for A...

> Longer term, I hope to improve the fence elimination of the ARM backend with > a kind of PRE algorithm. Both of these improvements to the ARM backend > should be fairly straightforward to port to the POWER architecture later, > and I hope to also do that. > > Any reason these couldn't be done at the IR level? I definitely agree here. At the time, it was a plausible idea

Hi everyone, The OpenMP standards committee has begun work to formalize their memory model, and define its relationship to the C/C++ memory models. A questionnaire has been put together (pasted below), and I'd like everyone's help in composing detailed answers to inform their decision-making process. While our OpenMP support is still in active development, many of these questions apply