search for: cp32

...g(regs, reg); printk("DOM%d: R%d = %#010"PRIx32" at %#010"PRIx32"\n", domid, reg, *r, regs->pc); break; @@ -518,7 +576,7 @@ static void do_cp15_32(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_cp32 cp32 = hsr.cp32; - uint32_t *r = &regs->r0 + cp32.reg; + uint32_t *r = select_user_reg(regs, cp32.reg); if ( !cp32.ccvalid ) { dprintk(XENLOG_ERR, "cp_15(32): need to handle invalid condition codes\n"); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c in...

...essor-ca15.h> +#include <asm/processor-ca7.h> #include <asm/asm_defns.h> #define ZIMAGE_MAGIC_NUMBER 0x016f2818 @@ -185,18 +186,36 @@ hyp: blo 1b skip_bss: - PRINT("- Setting up control registers -\r\n") - /* Read CPU ID */ - mrc CP32(r0, MIDR) - ldr r1, =(MIDR_MASK) - and r0, r0, r1 - /* Is this a Cortex A15? */ - ldr r1, =(CORTEX_A15_ID) - teq r0, r1 - bleq cortex_a15_init + /* Get processor specific proc info into r1 */ + mrc CP32(r0, MIDR) /* r...

From: Marc Carino <marc.ceeeee@gmail.com> Let Xen recognize the Broadcom Brahma-B15 CPU by adding the appropriate MIDR mask to the initialization phase. Further, ensure that the console output properly reports the CPU manufacturer as "Broadcom Corporation". Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> --- xen/arch/arm/arm32/proc-v7.S | 8 ++++++++

These series patch enable Allwinner A31(code name sun6i) support in assemble. with these patches, the cpu 0 of sun6i SOC could successful boot into the c environment. Bamvor Jian Zhang (4): xen/arm: introduce Cortex-A7 support xen/arm: introduce Allwinner sun6i SOC basic support xen/arm: enable early printk for sun6i xen/arm: enable switch to hyper mode for sun6i xen/arch/arm/Rules.mk

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

Hello, This series has been split into two patches, one for arm and one for x86. I figured that this was easier than doing it as a single combined patch, especially as the changes are functionally independent. x86 has been boot tested, but arm has not even been compile tested as I lack a suitable cross compiler. However, the changes are just text replacement, so I dont expect any issues. The

This patch series implements SMP boot for arch/arm, as far as getting all CPUs up and running the idle loop. Changes from v1: - moved barriers out of loop in udelay() - dropped broken GIC change in favour of explanatory comment - made the increment of ready_cpus atomic (I couldn''t move the increment to before signalling the next CPU because the PT switch has to happen between

See http://www.gossamer-threads.com/lists/xen/devel/297170 for some information on how to get this going. I''ve rebased and addressed the review comments. As before several of the patches are not to be applied because they can be done better using infrastructure from Julien''s "Allow Xen to boot with a raw Device Tree" patch. They are included for completeness. With