search for: coveringlanes

Displaying 3 results from an estimated 3 matches for "coveringlanes".

2013 May 16
0
[LLVMdev] Combining physical registers
On 5/16/2013 11:17 AM, Jakob Stoklund Olesen wrote: > > Would this TRI function solve your problem? >[...] > /// > /// Covering = getCoveringLanes(); > /// MaskA = getSubRegIndexLaneMask(SubA); > /// MaskB = getSubRegIndexLaneMask(SubB); > /// > /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by > /// SubB. > unsigned getCoveringLanes() const { return CoveringLanes; }...
2013 May 16
1
[LLVMdev] Combining physical registers
...ub-register is completely covered by the ssub_0 and ssub_1 lanes. /// This is related to the CoveredBySubRegs property on register definitions. /// /// This function returns a bit mask of lanes that completely cover their /// sub-registers. More precisely, given: /// /// Covering = getCoveringLanes(); /// MaskA = getSubRegIndexLaneMask(SubA); /// MaskB = getSubRegIndexLaneMask(SubB); /// /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by /// SubB. unsigned getCoveringLanes() const { return CoveringLanes; } /jakob
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are D0. The context here is an attempt to coalesce multiple loads/stores into fewer loads/stores