Displaying 11 results from an estimated 11 matches for "cortexm0".
2013 Feb 02
2
[LLVMdev] logic function optimization: IAR 1 - LLVM 0 ?
I gave the following function to IAR compiler (targeting CortexM0)
and to clang/LLVM 3.2 (clang -O3 -target thumbv6-eabi -emit-llvm)
int
calleeSave8(int in[]){
int out=0;
int i;
for(i=0;i<8;i++){
out ^=
in[i] & in[(i+1)%8];
}//expand to out =
(in[0]&in[1])^(in[1]&in[2])^(in[2]&in[3])^(in[3]&in[4])^(in[4]&in[5])^(in[5]&in[6])^...
2013 Feb 26
2
[LLVMdev] arm compiler benchmarks
Hi,
I didn't do any serious benchmarking but so far I never found
a case where LLVM does better than IAR on CortexM0, but I saw a lot of
cases where IAR output is better than LLVM...
That said I did not use
-Os or -Oz, I just used -O3.
A recurrent situation is that LLVM
push/pop one or two extra registers compared to IAR, I guess it does so
in order to comply with a standard ABI or something but in the world...
2013 Feb 27
2
[LLVMdev] arm compiler benchmarks
...chip like that.
>
> -Jim
>
> On Feb 26, 2013, at 2:11 PM, matic at nimp.co.uk <mailto:matic at nimp.co.uk>
> wrote:
>
>> Hi,
>>
>>
>> I didn't do any serious benchmarking but so far I never found a case
>> where LLVM does better than IAR on CortexM0, but I saw a lot of cases
>> where IAR output is better than LLVM...
>>
>> That said I did not use -Os or -Oz, I just used -O3.
>>
>> A recurrent situation is that LLVM push/pop one or two extra registers
>> compared to IAR, I guess it does so in order to comply...
2013 Feb 25
0
[LLVMdev] backend documentation
...uld be any interest in an annual (or
some
> reasonable interval) "workshop" sort of thing that teaches
backend
> development. That may be a better learning medium for this
material
> than a book.
>
> -- Sean Silva
--> I would join right
away! I am making a backend for CortexM0 to learn this black art. Even
though the ARM backend is here to show me the way, this is still quite
hard to get things right in a reasonable time. For example loading an
immediate value from a constant pool or implementing push/pop/pop_ret
were not an easy ride...
A workshop would be really usef...
2014 May 12
2
[LLVMdev] A Question to LLVM
Hi,
I want to use LLVM to compile a ARM-CortexM0 project on windows. But LLVM can't output ELF file on windows. An assert was thrown from LLVM. What can I do now? Thanks!
Steven.Q
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2013 Feb 04
0
[LLVMdev] logic function optimization: IAR 1 - LLVM 0 ?
Have you tried armv7?
-bw
On Feb 2, 2013, at 3:50 PM, matic at nimp.co.uk wrote:
> I gave the following function to IAR compiler (targeting CortexM0) and to clang/LLVM 3.2 (clang -O3 -target thumbv6-eabi -emit-llvm)
>
> int calleeSave8(int in[]){
> int out=0;
> int i;
> for(i=0;i<8;i++){
> out ^= in[i] & in[(i+1)%8];
> }//expand to out = (in[0]&in[1])^(in[1]&in[2])^(in[2]&in[3])^(...
2013 Feb 26
0
[LLVMdev] arm compiler benchmarks
...ot surprised that an embedded market focussed compiler like IAR is better tuned for a chip like that.
-Jim
On Feb 26, 2013, at 2:11 PM, matic at nimp.co.uk wrote:
> Hi,
>
>
> I didn't do any serious benchmarking but so far I never found a case where LLVM does better than IAR on CortexM0, but I saw a lot of cases where IAR output is better than LLVM...
>
> That said I did not use -Os or -Oz, I just used -O3.
>
> A recurrent situation is that LLVM push/pop one or two extra registers compared to IAR, I guess it does so in order to comply with a standard ABI or something...
2013 Feb 05
1
[LLVMdev] logic function optimization: IAR 1 - LLVM 0 ?
...ld be a target independent optimization isn't it ??
Cheers
Sebastien
On 2013-02-04 16:46, Bill Wendling wrote:
> Have you tried
armv7?
>
> -bw
>
> On Feb 2, 2013, at 3:50 PM,
matic at nimp.co.ukwrote:
>
>> I gave the following function to IAR
compiler (targeting CortexM0) and to clang/LLVM 3.2 (clang -O3 -target
thumbv6-eabi -emit-llvm) int calleeSave8(int in[]){ int out=0; int i;
for(i=0;i<8;i++){ out ^= in[i] & in[(i+1)%8]; }//expand to out =
(in[0]&in[1])^(in[1]&in[2])^(in[2]&in[3])^(in[3]&in[4])^(in[4]&in[5])^(in[5]&in[6])^(in[6]&...
2013 Feb 27
0
[LLVMdev] arm compiler benchmarks
...>> On Feb 26, 2013, at 2:11 PM, matic at nimp.co.uk <mailto:matic at nimp.co.uk>
>> wrote:
>>
>>> Hi,
>>>
>>>
>>> I didn't do any serious benchmarking but so far I never found a case
>>> where LLVM does better than IAR on CortexM0, but I saw a lot of cases
>>> where IAR output is better than LLVM...
>>>
>>> That said I did not use -Os or -Oz, I just used -O3.
>>>
>>> A recurrent situation is that LLVM push/pop one or two extra registers
>>> compared to IAR, I guess it d...
2013 Feb 03
1
[LLVMdev] Chain and glue operands should occur at end of operand list
Hi,
I got that message from a call to InstrEmitter::AddOperand. I
am writing a back end for CortexM0 (for self teaching purposes), I am
working on LDR with immediate offset instruction.
In the ARM backend,
if the offset is 0, the following code is executed by the function
ARMDAGToDAGISel::SelectThumbAddrModeImm5S
Base =
N.getOperand(0);
OffImm = CurDAG->getTargetConstant(0, MVT::i32);
If...
2013 Feb 27
2
[LLVMdev] arm compiler benchmarks
...at.
>
> -Jim
>
> On Feb 26, 2013, at 2:11 PM, matic at nimp.co.uk <mailto:matic at nimp.co.uk<matic at nimp.co.uk>
> >
> wrote:
>
> Hi,
>
>
> I didn't do any serious benchmarking but so far I never found a case
> where LLVM does better than IAR on CortexM0, but I saw a lot of cases
> where IAR output is better than LLVM...
>
> That said I did not use -Os or -Oz, I just used -O3.
>
> A recurrent situation is that LLVM push/pop one or two extra registers
> compared to IAR, I guess it does so in order to comply with a standard
> ABI...