search for: cortexa8itinerari

...icro-architectures can be described. I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages. See /include/llvm/Target/TargetInstrItineraries.h for some information. The CortexA8Itineraries description in ARMScheduleV7.td is where I am using these new features to model the Cortex-A8. All of this is a work in progress... I suppose when I finish I will write up something describing the new Itinerary model and how to use it... David On Aug 18, 2009, at 1:11 AM, Carter Cheng w...

...getInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost = 0) const; Example: def CortexA8Model : SchedMachineModel { ... let Itineraries = CortexA8Itineraries; } If you don't actually have any itineraries defined in you target's Schedule.td files, you need to define some dummy itinerary with at least one entry. Something like this may work (I haven't tried it). def IIC_Default : InstrItinClass; def MyItineraries : ProcessorItineraries&lt...

Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen. --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote: > From: Carter Cheng <carter_cheng at yahoo.com> > Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc. > To: llvmdev at cs.uiuc.edu > Date:

Here is a one-line patch to support the cortex-m3. For those who plan the features for ARM, the new cortex-m0 implements only a subset of the Thumb2 instructions. I still have yet to see a document that details what's in the subset. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: arm.diff URL:

...that > details what's in the subset. > > > Index: ARM.td > =================================================================== > --- ARM.td      (revision 89605) > +++ ARM.td      (working copy) > @@ -106,6 +106,7 @@ >  def : Processor<"cortex-a8",        CortexA8Itineraries, >                 [ArchV7A, FeatureThumb2, FeatureNEON]>; >  def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>; > +def : ProcNoItin<"cortex-m3",       [ArchV7A, FeatureThumb2]>; > >  //===---------------------------------...

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things. Thanks in advance, Carter.