search for: corei7

Hi Andrew, I think I diluted my question. My question was not related to MCJIT. I ran the following 4 scenarios: (1)gcc -mcpu=corei7 tetris.c -o tetris (2)gcc -mcpu=athlon64 tetris.c -o tetris (3)clang -march=corei7 tetris.c -o tetris (4)clang -march=athlon64 tetris.c -o tetris In (1) and (2), I see difference in order of instructions in the output binaries, which I expected because every CPU has different micro-architecture, a...

...d to see if there are any performance gains as the compiler can detect the target CPU at runtime. But, I didn't see any improvement (I compile with -no-mmx and -no-sse). I then tried an experiment, where I compiled the program with clang-3.3, with and without specifying the target cpu as "corei7". I was shocked to see that the only difference in the two binaries were related to "Instruction Set Extensions". Further I tried the same experiment with gcc, and saw that the instructions were shuffled around in the binary. I expected this, because every CPU differs in some way or...

...s the owner of the x86 backend, and he can probably give you a more complete answer than I could. Thanks, Andy From: Varun Agrawal [mailto:vagrawal at cs.stonybrook.edu] Sent: Friday, October 11, 2013 8:48 PM To: Kaylor, Andrew; llvmdev at cs.uiuc.edu Subject: RE: Building for a specific target, corei7 Hi Andrew, I think I diluted my question. My question was not related to MCJIT. I ran the following 4 scenarios: (1)gcc -mcpu=corei7 tetris.c -o tetris (2)gcc -mcpu=athlon64 tetris.c -o tetris (3)clang -march=corei7 tetris.c -o tetris (4)clang -march=athlon64 tetris.c -o tetris In (1) and (2),...

...al targets. However, you can specify the CPU by calling setCPU() on the EngineBuilder object before creating your execution engine. (You can use sys::getHostCPUName() to figure out what CPU you are running on and that will further detect AVX support, which you don't get with the general "corei7" cpu flag.) I would expect that if you do that it would generate similar code to clang. -Andy From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Varun Agrawal Sent: Thursday, October 10, 2013 10:52 PM To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] Build...

Noticed something I thought I would share so that others don't scratch their head wondering about it if they try the same. I updated my system to Oneiric, and decided to recompile Wine. I tried making use of the corei7 optimizations in gcc 4.6 and found that, while a lot of stuff worked (ex. Steam), other things (like DirectX games) did not. So, as always... don't expect things to work when turning on optimizations.

...ad it gets lowered into two shufps instructions. Example: ;;; define <4 x float> @foo(<4 x float> %A, <4 x float> %B) { %1 = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7> ret <4 x float> %1 } ;;; llc (-mcpu=corei7-avx): vblendps $10, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[5],xmm0[2],xmm1[7] llc -x86-experimental-vector-shuffle-lowering (-mcpu=corei7-avx): vshufps $-40, %xmm0, %xmm1, %xmm0 # xmm0 = xmm1[0,2],xmm0[1,3] vshufps $-40, %xmm0, %xmm0, %xmm0 # xmm0[0,2,1,3] 2) On SSE4.1, we should try...

..." -use-mcjit libengine.bc > LLVM ERROR: Inline asm not supported by this streamer because we don't have an asm parser for this target I also tried other variations of the call with the same result: > $lli -entry-function="ISimEngine_GetVersion" -use-mcjit -mattr=+avx -mcpu=corei7-avx libengine.bc I updated my program looking at lli.cpp and it also gave the same error as above. The info from lli --version is below: > $lli --version > LLVM (http://llvm.org/): > LLVM version 3.2svn > Optimized build with assertions. > Built May 7 2012 (10:54:43). >...

...> Example: > ;;; > define <4 x float> @foo(<4 x float> %A, <4 x float> %B) { > %1 = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 0, > i32 5, i32 2, i32 7> > ret <4 x float> %1 > } > ;;; > > llc (-mcpu=corei7-avx): > vblendps $10, %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[5],xmm0[2],xmm1[7] > > llc -x86-experimental-vector-shuffle-lowering (-mcpu=corei7-avx): > vshufps $-40, %xmm0, %xmm1, %xmm0 # xmm0 = xmm1[0,2],xmm0[1,3] > vshufps $-40, %xmm0, %xmm0, %xmm0 # xmm0[0,2,1,3] >...

...; Here is another test. > > When looking at the AVX codegen, I noticed that, when using the new > shuffle lowering, we no longer emit a single vbroadcastss in the case > where the shuffle performs a splat of a scalar float loaded from > memory. > > For example: > (with -mcpu=corei7-avx -x86-experimental-vector-shuffle-lowering) > vmovss (%rdi), %xmm0 > vpermilps $0, %xmm0, %xmm0 # xmm0 = xmm0[0,0,0,0] > > Instead of: > (with -mcpu=corei7-avx) > vbroadcastss (%rdi), %xmm0 > > I have attached a small reproducible for it. > > Basically, the...

Johannes, I tried the last one and it gave me this: error: unknown target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,...

...ject: Re: [llvm-dev] Generating object files more efficiently Johannes, I tried the last one and it gave me this: error: unknown target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,...

...LLVM ERROR: Inline asm not supported by this streamer because we don't > > have an asm parser for this target > > I also tried other variations of the call with the same result: > > $lli -entry-function="ISimEngine_GetVersion" -use-mcjit -mattr=+avx > > -mcpu=corei7-avx libengine.bc > > I updated my program looking at lli.cpp and it also gave the same error as > above. The info from lli --version is below: > > > $lli --version > > LLVM (http://llvm.org/): > > LLVM version 3.2svn > > Optimized build with assertions. &gt...

Nadav, Please forgive my ignorance, but 'opt -mcpu=corei7 -loop-vectorize -S -debug double.ll' doesn't appear to make a difference. In fact it seems to be ignored as garbage values for -mcpu don't raise an error. Am I overlooking something else also? Many Thanks, Josh On Thu, May 9, 2013 at 6:06 PM, Nadav Rotem <nrotem at apple.com>...

Hi Josh, This line works for me: opt file.ll -loop-vectorize -S -o - -mtriple=x86_64 -mcpu=corei7-avx -debug You need to specify the triple on the command line if it is not inside the module. Thanks, Nadav On May 9, 2013, at 5:53 PM, Joshua Klontz <josh.klontz at gmail.com> wrote: > Nadav, > > Please forgive my ignorance, but 'opt -mcpu=corei7 -loop-vectorize -S -debu...

...ine asm not supported by this streamer because we don't >>> have an asm parser for this target >> >> I also tried other variations of the call with the same result: >>> $lli -entry-function="ISimEngine_GetVersion" -use-mcjit -mattr=+avx >>> -mcpu=corei7-avx libengine.bc >> >> I updated my program looking at lli.cpp and it also gave the same error as >> above. The info from lli --version is below: >> >>> $lli --version >>> LLVM (http://llvm.org/): >>> LLVM version 3.2svn >>> Optimize...

On Tue, Sep 23, 2014 at 2:35 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > If you don’t want to spend time on this, I’d be happy to create a > candidate patch for review? I’ve been unclear if you were taking patches > for your shuffle work prior to it becoming the default. While I'm happy to work on it, I'm even more happy to have patches. =D -------------- next

...iciently > > > > Johannes, > > > I tried the last one and it gave me this: > > > error: unknown target CPU 'XYZ' > note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, > silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, > westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, > core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, > cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, > athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-ss...

...al llvm optimizations. This probably means that the generated tests are currently too simple for the higher-level optimizations. The command line below generates a random ll file, and llc compiles this file. It often crashes. ./llvm-stress -seed $RANDOM -o tmp.ll -size 1000 ; ./llc tmp.ll -mcpu=corei7-avx -mattr=+avx -o /dev/null The "-seed" flag sets the initial seed to be used by the random function. I implemented a simple portable 'random' function so that the result should be identical on all platforms. The initial seed also appears in the name of the generated function....

Sorry for the delays here. I am running our benchmark suite and will have data in a day or so. On Jun 13, 2013 9:40 PM, "Nadav Rotem" <nrotem at apple.com> wrote: > Hi, > > Last week I wrote llvm-dev and presented data that shows how enabling the > vectorizer on -Os can improve the performance of many workloads and that it > has negligible effects on code size. I

...define <4 x float> @baz(<4 x float> %A, <4 x float> %B) { >> %1 = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 4, >> i32 1, i32 2, i32 3> >> ret <4 x float> %1 >> } >> ;;; >> >> llc (-mcpu=corei7-avx): >> vmovss %xmm1, %xmm0, %xmm0 >> >> llc -x86-experimental-vector-shuffle-lowering (-mcpu=corei7-avx): >> vinsertps $0, %xmm1, %xmm0, %xmm0 # xmm0 = xmm1[0],xmm0[1,2,3] > > > So, this is hard. I think we should do this in MC after register allocation > b...