Displaying 8 results from an estimated 8 matches for "copymi".
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2020 Jun 18
2
[ARM] Thumb code-gen for 8-bit imm arguments results in extra reg copies
...ld update cpsr n/z flags, but
since it's overwritten by following instructions, it's marked as dead
in both cases ?
The patch just checks that only one def is live and remaining defs of
DefMI are dead in reMaterializeTrivialDef, in which case I assume it
should be safe to
propagate value of CopyMI into DefMI ?
If reMaterializeTrivialDef is not the right place to handle the
transform, could you please suggest where should I look for adding it
?
Thanks!
Regards,
Prathamesh
>
> Cheers.
>
> Tim.
2009 Jan 09
2
[LLVMdev] implicit CC register Defs cause "physreg was not killed in defining block!" assert
...e all arithmetic/logic instructions affect it ('let Defs = [CCFLAGS] in...' in InstrInfo.td) I run into
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
// and never used.
assert(!CopyMI && "physreg was not killed in defining block!");
in LiveIntervals::handlePhysicalRegisterDef().
The dump() of the MBB from the debugger looks like the following:
entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2:
Predecessors according to CFG: 0x12bc290 (#0) 0x...
2012 Feb 16
1
[LLVMdev] LLVM: MachineCopyPropagation.cpp
...a1l
, as input to MachineCopyPropagation.
The second copy is illegally erased! This is wrong, because it is the low part of a1 that is copied to the high part of a0.
At a first glance, it seems that
if (!ReservedRegs.test(Def) &&
(!ReservedRegs.test(Src) || NoInterveningSideEffect(CopyMI, MI)) &&
(SrcSrc == Def || TRI->isSubRegister(SrcSrc, Def))) {
...
(erase COPY)
, should be extended to
...
(SrcSrc == Def || (TRI->isSubRegister(SrcSrc, Def) && isMatchingSubRegIdx(%a0, %a0h, %a1, %a1l)))) {
, where isMatchingSubRegIdx (or what...
2012 Oct 20
0
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote:
> below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
> The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
>
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...:joinVirtRegs (this=0x21b62b0, CP=...) at RegisterCoalescer.cpp:1861
#7 0x00000000010cb646 in (anonymous namespace)::RegisterCoalescer::joinIntervals (this=0x21b62b0, CP=...) at RegisterCoalescer.cpp:1883
#8 0x00000000010c84b4 in (anonymous namespace)::RegisterCoalescer::joinCopy (this=0x21b62b0, CopyMI=0x21e8cf8, Again=@0x7fffffffd7a2: false) at RegisterCoalescer.cpp:1002
#9 0x00000000010cb830 in (anonymous namespace)::RegisterCoalescer::copyCoalesceWorkList (this=0x21b62b0, From=0) at RegisterCoalescer.cpp:1924
#10 0x00000000010cb9f7 in (anonymous namespace)::RegisterCoalescer::copyCoalesceInMB...
2020 Jun 16
2
[ARM] Thumb code-gen for 8-bit imm arguments results in extra reg copies
Hi,
For the following test-case:
void foo(unsigned, unsigned);
void f()
{
foo(10, 20);
foo(10, 20);
}
clang --target=arm-linux-gnueabi -mthumb -O2 generates:
push {r4, r5, r7, lr}
movs r4, #10
movs r5, #20
movs r0, r4
movs r1, r5
bl foo
movs r0, r4
movs r1, r5
bl foo
pop {r4,
2009 Jan 09
0
[LLVMdev] implicit CC register Defs cause "physreg was not killed in defining block!" assert
...t it ('let Defs
> = [CCFLAGS] in...' in InstrInfo.td) I run into
>
> // The only case we should have a dead physreg here without a
> killing or
> // instruction where we know it's dead is if it is live-in to the
> function
> // and never used.
> assert(!CopyMI && "physreg was not killed in defining block!");
>
> in LiveIntervals::handlePhysicalRegisterDef().
>
> The dump() of the MBB from the debugger looks like the following:
>
> entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2:
> Predecessors acco...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
Hi,
below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
I don't know if it's a bug of the pass, or if my backend should do something