search for: copyfromreg

...in operations (like sdiv). We recently ran into a problem where these operations that are expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0,...

...2016 at 11:34 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:32 PM, Rail Shafigulin wrote: > >> I think this is where I'm loosing the "thread". Based on what I'm seeing >> SET_FLAG has three operands, the first of which is a CopyFromReg. So how >> come the pattern is SET_FLAG %vreg5, 3, 20 and not SET_FLAG CopyFromReg, >> 3, 20? In other words how do we go from CopyFromReg to %vreg5? >> > > CopyFromReg is a "helper" instruction meaning "use the value from this > vreg". Values that ar...

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 t15: i32,...

On Thu, Feb 18, 2016 at 11:48 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:40 PM, Rail Shafigulin wrote: > >> >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] >> [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1] >> >> Based on the code above, CopyFromReg is a node at address 0x3283608, >> returns i32, is of type chain and takes two inputs, the second of which >> is a...

...s are being >> legalized. >> So this is my intial basic block. The area of concern is the last three >> instructions. I will pick and choose debug output to keep this small. >> >> SelectionDAG has 36 nodes: >> t0: ch = EntryToken >> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 >> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6, t9 >> t12: i32,ch = CopyFromR...

...> wrote: >> >> On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote: >> >> >> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG >> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11] >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] >> [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1] >> 0x3283710: i32 = Constant<3> [ID=2] >> 0x3283e48: i32 = Constant<20> [ID=8] >> In function: fib >> >>...

Hello, I have a kernel that's swizzling a vector inside a loop. The vector was created before the loop. The first node in the dag is an extract subvector which calls into SplitVectorOp. The issue is that the node passed to it comes from a CopyFromReg and SplitVectorOp doesn't know what to do. Is there a reason why SplitVectorOp doesn't handle CopyFromReg nodes? If not, can I submit a patch to add support? Thanks, Javier

...0xd1b220: f64 = add 0xd1b120, 0xd1a210 [ORD=4] [ID=27] 0xd1b120: f64 = add 0xd1b020, 0xd1a010 [ORD=3] [ID=26] 0xd1b020: f64 = add 0xd1af20, 0xd19e10 [ORD=2] [ID=25] 0xd1af20: f64 = add 0xd19a10, 0xd19c10 [ORD=1] [ID=24] 0xd19a10: f64,ch = CopyFromReg 0xcee028, 0xd19910 [ORD=1] [ID=14] 0xd19c10: f64,ch = CopyFromReg 0xcee028, 0xd19b10 [ORD=1] [ID=15] 0xd19e10: f64,ch = CopyFromReg 0xcee028, 0xd19d10 [ORD=2] [ID=16] 0xd19d10: f64 = Register %vreg2 [ORD=2] [ID=3] 0xd1a010: f64,ch...

Hi Javier, > I have a kernel that's swizzling a vector inside a loop. The vector was > created before the loop. The first node in the dag is an extract subvector > which calls into SplitVectorOp. The issue is that the node passed to it > comes from a CopyFromReg and SplitVectorOp doesn't know what to do. Is > there a reason why SplitVectorOp doesn't handle CopyFromReg nodes? If not, > can I submit a patch to add support? a testcase would be helpful. Ciao, Duncan.

...RX32, which also contains the high 32-bit part registers. I have tried to find a simple way to constrain the register class of such copies (also at -O0), but this turned out to not be quite simple. Just selecting a pseudo instruction with a custom inserter does not seem to work since CopyToReg/CopyFromReg have special handlings in InstrEmitter. I then tried in SystemZDAGToDAG.cpp to select a CopyToReg to (CopyToReg COPY_TO_REGCLASS), which worked fine. But I could not get the same results with CopyFromReg. (COPY_TO_REGCLASS CopyFromReg) only resulted in a later COPY into GR32, but the COPY from...

I have a CopyToReg that is moving a 16bit reg to a 32bit reg, it's currently being mapped out as a simple mov (not an ext), I would like to change that to an ext. It seemed that the SelDAG was the easiest and cleanest way to do this. I can change the mov to an extension MI in the .td file; however, I can't tell at that point whether it's a sext or a zext, so it seemed the SelDAG was

In my target I want to have mem-mem operations. But PHI instructions use virtual registers and gets converted to a series of CopyFromReg and CopyToReg instructions. These DAGs end up using physical registers. My first approach was to spill the virtual register to force a mem-mem operation. But I was unable to do this using LowerOperation() and setOperationAction(ISD::CopyToReg, MVT::i32, Custom); Any ideas would be appreciated. I...

...erated a following error: fatal error: error in backend: Cannot select: 0x6a84dc8: i32 = extract_vector_elt 0x6a85388, 0x6a813b0 [ORD=9] [ID=16] 0x6a85388: v4i32 = add 0x6a81098, 0x6a81e00 [ORD=8] [ID=15] 0x6a81098: v4i32 = add 0x6a81bf0, 0x6a84168 [ORD=6] [ID=12] 0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5] [ID=8] 0x6a819e0: v4i32 = Register %vreg4 [ID=1] 0x6a84168: v4i32 = vector_shuffle 0x6a81bf0, 0x6a857a8<2,3,u,u> [ORD=5] [ID=10] 0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5] [ID=8] 0x6a819e0: v4i32 = Register %vreg...

They are all Alpha/PowerPC codegen related. Running /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/dg.exp ... FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll: NODE: 0x8582a40: i32,ch = CopyFromReg 0x8582980:1, 0x85829c0 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/bsr.ll: NODE: 0x85823c0: i32,ch = CopyFromReg 0x8582300, 0x8582340 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/ctlz.ll: NODE: 0x8582340: i8,...

...1b120, 0xd1a210 [ORD=4] [ID=27] > 0xd1b120: f64 = add 0xd1b020, 0xd1a010 [ORD=3] [ID=26] > 0xd1b020: f64 = add 0xd1af20, 0xd19e10 [ORD=2] [ID=25] > 0xd1af20: f64 = add 0xd19a10, 0xd19c10 [ORD=1] [ID=24] > 0xd19a10: f64,ch = CopyFromReg 0xcee028, 0xd19910 [ORD=1] > [ID=14] > > 0xd19c10: f64,ch = CopyFromReg 0xcee028, 0xd19b10 [ORD=1] > [ID=15] > > 0xd19e10: f64,ch = CopyFromReg 0xcee028, 0xd19d10 [ORD=2] > [ID=16] > 0xd19d10: f64 = Register %vreg2 [ORD=...

Is there any way to get it to delay this optimization where it goes from this: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64...

...via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote: > >> >> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG >> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11] >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1] >> 0x3283710: i32 = Constant<3> [ID=2] >> 0x3283e48: i32 = Constant<20> [ID=8] >> In function: fib >> >> As far as I can understand LLVM cannot select it because...

...mson at gmail.com> > wrote: > >> Is there any way to get it to delay this optimization where it goes from >> this: >> >> Initial selection DAG: BB#0 'bclr64:entry' >> SelectionDAG has 14 nodes: >> t0: ch = EntryToken >> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 >> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 >> t6: i64 = sub t4, Constant:i64<1> >> t7: i64 = shl Constant:i64<1>, t6 >> t9: i64 = xor t7, Constant:i64<-1> >> t10: i64 = and t2, t...

...x170dc60, 0x170ec00, 0x170ef00 [ID=19] 0x170f000: ch = TokenFactor 0x170e560, 0x170e760, 0x170e960 [ID=18] 0x170e560: ch = CopyToReg 0x16d5748, 0x170e460, 0x170df60 [ID=15] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e460: i16 = Register %reg16384 [ID=5] 0x170df60: i16,ch = CopyFromReg 0x16d5748, 0x170de60 [ID=12] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170de60: i16 = Register %reg16388 [ID=2] 0x170e760: ch = CopyToReg 0x16d5748, 0x170e660, 0x170e160 [ID=16] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e660: i16 = Register %reg16385 [ID=6]...

...src, i16 %i.0 %0 = load i8, i8* %arrayidx, align 1, !tbaa !2 %arrayidx1 = getelementptr inbounds i8, i8* %dest, i16 %i.0 store i8 %0, i8* %arrayidx1, align 1, !tbaa !2 %inc = add nuw nsw i16 %i.0, 1 br label %for.cond This gets converted into this by llc: Creating new node: t2: i16,ch = CopyFromReg t0, Register:i16 %3 Creating new node: t4: i16,ch = CopyFromReg t0, Register:i16 %0 Creating new node: t5: i16 = add t2, t4 Creating constant: t6: i16 = Constant<0> Creating new node: t7: i16 = undef Creating new node: t8: i8,ch = load<(load 1 from %ir.scevgep1, !tbaa !2)> t0, t5, undef...