search for: convergingschedul

Hi, In ConvergingScheduler::checkResourceLimits on line 1535 of MachineScheduler.cpp setLatencyPolicy is called as follows: // Set ReduceLatency to true if needed. Bot.setLatencyPolicy(TopCand.Policy); Top.setLatencyPolicy(BotCand.Policy); So the Bot scheduling boundary is used to set the latency policy of the...

...ons at the same time. > In the TableGen definitions, should I do: > > def HWVMEM : ProcResource<15>; > or > > let BufferSize = 15 in { > def HWVMEM : ProcResource<1>; > } For in-order processors you always want BufferSize=0. In the current generic scheduler (ConvergingScheduler) it's effectively a boolean that specifies inorder vs OOO. (I have code that models the buffers in an OOO processor, but I think it’s too heavy-weight to go in the scheduler. Maybe someday it can be an analysis tool.) let BufferSize = 0 { def HWVMEM : ProcResource<15>; } Now since y...

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

...for top-down scheduling. If the instruction was in multiple ready Q's, then you may attempt to schedule it multiple times. You can avoid this by checking Su->isScheduled in your Strategy's pickNode. See InstructionShuffler::pickNode for an example. I don't see an equivalent check in ConvergingScheduler, but there probably should be. Another possibility to consider is something strange with DebugValues, which I haven't tested much. I reproduced the same assert on arm and filed PR13719. I'm not sure yet if it's exactly the same issue, but we can move the discussion there. We need a...

...ling. If the instruction was in multiple ready Q's, then you > may attempt to schedule it multiple times. You can avoid this by > checking Su->isScheduled in your Strategy's pickNode. See > InstructionShuffler::pickNode for an example. I don't see an equivalent > check in ConvergingScheduler, but there probably should be. > > Another possibility to consider is something strange with DebugValues, > which I haven't tested much. > > I reproduced the same assert on arm and filed PR13719. I'm not sure yet > if it's exactly the same issue, but we can move th...

...tion was in multiple ready Q's, then you > > may attempt to schedule it multiple times. You can avoid this by > > checking Su->isScheduled in your Strategy's pickNode. See > > InstructionShuffler::pickNode for an example. I don't see an equivalent > > check in ConvergingScheduler, but there probably should be. > > > > Another possibility to consider is something strange with DebugValues, > > which I haven't tested much. > > > > I reproduced the same assert on arm and filed PR13719. I'm not sure yet > > if it's exactly the sa...

Andy, I've described that issue (see below) when you were out of town... I think I am getting more context on it. Please take a look... So, in short, when the new MI scheduler performs move of an instruction, it does something like this: // Move the instruction to its new location in the instruction stream. MachineInstr *MI = SU->getInstr(); if (IsTopNode) {

...ling. If the instruction was in multiple ready Q's, then you > may attempt to schedule it multiple times. You can avoid this by > checking Su->isScheduled in your Strategy's pickNode. See > InstructionShuffler::pickNode for an example. I don't see an equivalent > check in ConvergingScheduler, but there probably should be. > > Another possibility to consider is something strange with DebugValues, > which I haven't tested much. > > I reproduced the same assert on arm and filed PR13719. I'm not sure yet > if it's exactly the same issue, but we can move the...

...was in multiple ready Q's, > > then you may attempt to schedule it multiple times. You can avoid > this > > by checking Su->isScheduled in your Strategy's pickNode. See > > InstructionShuffler::pickNode for an example. I don't see an > > equivalent check in ConvergingScheduler, but there probably should > be. > > > > Another possibility to consider is something strange with > DebugValues, > > which I haven't tested much. > > > > I reproduced the same assert on arm and filed PR13719. I'm not sure > > yet if it's exac...

...ling. If the instruction was in multiple ready Q's, then you > may attempt to schedule it multiple times. You can avoid this by > checking Su->isScheduled in your Strategy's pickNode. See > InstructionShuffler::pickNode for an example. I don't see an equivalent > check in ConvergingScheduler, but there probably should be. > > Another possibility to consider is something strange with DebugValues, > which I haven't tested much. > > I reproduced the same assert on arm and filed PR13719. I'm not sure yet > if it's exactly the same issue, but we can move the...

...y Q's, >> > then you may attempt to schedule it multiple times. You can avoid >> this >> > by checking Su->isScheduled in your Strategy's pickNode. See >> > InstructionShuffler::pickNode for an example. I don't see an >> > equivalent check in ConvergingScheduler, but there probably should >> be. >> > >> > Another possibility to consider is something strange with >> DebugValues, >> > which I haven't tested much. >> > >> > I reproduced the same assert on arm and filed PR13719. I'm not sure &g...

...> then you may attempt to schedule it multiple times. You can avoid > >> this > >> > by checking Su->isScheduled in your Strategy's pickNode. See > >> > InstructionShuffler::pickNode for an example. I don't see an > >> > equivalent check in ConvergingScheduler, but there probably should > >> be. > >> > > >> > Another possibility to consider is something strange with > >> DebugValues, > >> > which I haven't tested much. > >> > > >> > I reproduced the same assert on arm and...

...tion was in multiple ready Q's, then you > > may attempt to schedule it multiple times. You can avoid this by > > checking Su->isScheduled in your Strategy's pickNode. See > > InstructionShuffler::pickNode for an example. I don't see an equivalent > > check in ConvergingScheduler, but there probably should be. > > > > Another possibility to consider is something strange with DebugValues, > > which I haven't tested much. > > > > I reproduced the same assert on arm and filed PR13719. I'm not sure yet > > if it's exactly the sa...