search for: conv8

...= load i8* %arrayidx1, align 1, !tbaa !0 %conv2 = zext i8 %2 to i32 %3 = load i8** @q, align 4, !tbaa !2 <<< Can this load be bypassed by the store below? %4 = load i8* %3, align 1, !tbaa !0 %conv5 = zext i8 %4 to i32 %add = add i32 %conv2, %conv %add7 = add i32 %add, %conv5 %conv8 = trunc i32 %add7 to i8 store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the above load? ret void } At the point of enquiry I have the following (lowered) instructions: x3df7900: i32,ch = LDw_GP_V4 0x3df4c70, 0x3df5470<Mem:LD4[@q](tbaa=!"any pointer")...

...tbaa !0 >  %conv2 = zext i8 %2 to i32 >  %3 = load i8** @q, align 4, !tbaa !2 <<< Can this load be bypassed by the > store below? >  %4 = load i8* %3, align 1, !tbaa !0 >  %conv5 = zext i8 %4 to i32 >  %add = add i32 %conv2, %conv >  %add7 = add i32 %add, %conv5 >  %conv8 = trunc i32 %add7 to i8 >  store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the > above load? Err, are you sure you're asking the right question? Given the loads you're pointing at, you're asking whether &s and &q alias. -Eli

...000e-01 %9 = load float* %y, align 4 %conv3 = fpext float %9 to double %mul4 = fmul double %conv3, 1.700000e-01 %add = fadd double %mul, %mul4 %10 = load float* %z, align 4 %conv5 = fpext float %10 to double %mul6 = fmul double %conv5, 1.600000e-01 %add7 = fadd double %add, %mul6 %conv8 = fptrunc double %add7 to float store float %conv8, float* %res, align 4 %11 = load float* %res, align 4 %12 = load i32* %i, align 4 %idxprom = sext i32 %12 to i64 %arrayidx9 = getelementptr inbounds float* %3, i64 %idxprom store float %11, float* %arrayidx9, align 4 br label %for.inc...

Hi Jochen, > My llvm version is 3.0 release. > I have a module generated by clang. When I optimize it, I first add an > inlining pass (llvm::createFunctionInliningPass), then these passes: > - own FunctionPass > - llvm::createPromoteMemoryToRegisterPass > - llvm::createInstructionCombiningPass > - llvm::createDeadInstEliminationPass > - llvm::createDeadStoreEliminationPass

...32> %a, i32 0 %vecext1 = extractelement <4 x i32> %a, i32 1 %vecext4 = extractelement <4 x i32> %b, i32 2 %vecext7 = extractelement <4 x i32> %b, i32 3 %conv = sitofp i32 %vecext to float %conv2 = sitofp i32 %vecext1 to float %conv5 = sitofp i32 %vecext4 to float %conv8 = sitofp i32 %vecext7 to float %vecinit = insertelement <4 x float> undef, float %conv, i32 0 %vecinit3 = insertelement <4 x float> %vecinit, float %conv2, i32 1 %vecinit6 = insertelement <4 x float> %vecinit3, float %conv5, i32 2 %vecinit9 = insertelement <4 x float&gt...

...t* %y, align 4 > %conv3 = fpext float %9 to double > %mul4 = fmul double %conv3, 1.700000e-01 > %add = fadd double %mul, %mul4 > %10 = load float* %z, align 4 > %conv5 = fpext float %10 to double > %mul6 = fmul double %conv5, 1.600000e-01 > %add7 = fadd double %add, %mul6 > %conv8 = fptrunc double %add7 to float > store float %conv8, float* %res, align 4 > %11 = load float* %res, align 4 > %12 = load i32* %i, align 4 > %idxprom = sext i32 %12 to i64 > %arrayidx9 = getelementptr inbounds float* %3, i64 %idxprom > store float %11, float* %arrayidx9, align 4 &...

Hi! My llvm version is 3.0 release. I have a module generated by clang. When I optimize it, I first add an inlining pass (llvm::createFunctionInliningPass), then these passes: - own FunctionPass - llvm::createPromoteMemoryToRegisterPass - llvm::createInstructionCombiningPass - llvm::createDeadInstEliminationPass - llvm::createDeadStoreEliminationPass - new llvm::DominatorTree() - new

...32> %a, i32 1 >> %vecext4 = extractelement <4 x i32> %b, i32 2 >> %vecext7 = extractelement <4 x i32> %b, i32 3 >> %conv = sitofp i32 %vecext to float >> %conv2 = sitofp i32 %vecext1 to float >> %conv5 = sitofp i32 %vecext4 to float >> %conv8 = sitofp i32 %vecext7 to float >> %vecinit = insertelement <4 x float> undef, float %conv, i32 0 >> %vecinit3 = insertelement <4 x float> %vecinit, float %conv2, i32 1 >> %vecinit6 = insertelement <4 x float> %vecinit3, float %conv5, i32 2 >> %vecin...

I have added a few PPC-specific DAG combines in the past that follow this pattern on specific operations. Now that it appears that this would be useful to do on yet another operation, I'm wondering what people think about doing this in the target-independent DAG Combiner for any legal/custom operation on the target. TL; DR; The generic pattern would look like this: (build_vector (op

> Has anybody debugged LLVM IR with GDB? I'm using dragonegg to transform C > into IR, then applying my optimizations. Passing "-g" to dragonegg doesn't > seem to work since it generates debug info for the C code, not the IR. I > really need GDB (lli doesn't solve my problems) in order to debug > multi-threaded and multi-process MPI code. > > More

...while(i-- > argc) (gdb) n 14 while(j++ < i) k += j; (gdb) n 102 %77 = load i8** @global, align 8 (gdb) n 105 %79 = load i32* %78, align 4 (gdb) n 106 %cmp7.i.i.i = icmp ne i32 %79, 0 (gdb) n 108 call void @llvm.memset.p0i8.i64(i8* %add.ptr.i.i.i.i86, i8 %conv8.i.i.i, i64 4, i32 1, i1 false) nounwind (gdb) n 14 while(j++ < i) k += j; (gdb) n 15 while(j-- > 0) k *= k + j; (gdb) n 95 %69 = load i8** @global, align 8 (gdb) n 98 %71 = load i32* %70, align 4 (gdb) The pass itself is rather simple--the hard problem it solv...

Hi all, Has anybody debugged LLVM IR with GDB? I'm using dragonegg to transform C into IR, then applying my optimizations. Passing "-g" to dragonegg doesn't seem to work since it generates debug info for the C code, not the IR. I really need GDB (lli doesn't solve my problems) in order to debug multi-threaded and multi-process MPI code. More clearly, if I have a file