Displaying 13 results from an estimated 13 matches for "conv4".
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conv
2012 Feb 28
1
[LLVMdev] How to vectorize a vector type cast?
...uitofp i8 %1 to float
%vecinit = insertelement <4 x float> undef, float %conv, i32 0
%2 = extractelement <4 x i8> %0, i32 1
%conv2 = uitofp i8 %2 to float
%vecinit3 = insertelement <4 x float> %vecinit, float %conv2, i32 1
%3 = extractelement <4 x i8> %0, i32 2
%conv4 = uitofp i8 %3 to float
%vecinit5 = insertelement <4 x float> %vecinit3, float %conv4, i32 2
%4 = extractelement <4 x i8> %0, i32 3
%conv6 = uitofp i8 %4 to float
%vecinit7 = insertelement <4 x float> %vecinit5, float %conv6, i32 3
ret <4 x float> %vecinit7
Which...
2012 Oct 08
3
[LLVMdev] Multiply i8 operands promotes to i32
...C code:
void
(const u_int16_t in_data, u_int16_t* out)
{
u_int8_t kk = in_data&0xFF;
u_int16_t kk16 = kk * kk;
*out = kk16;
}
LLVM:
%1 = load i8* %kk, align 1
%conv2 = zext i8 %1 to i32
%2 = load i8* %kk, align 1
%conv3 = zext i8 %2 to i32
%mul = mul nsw i32 %conv2, %conv3
%conv4 = trunc i32 %mul to i16
store i16 %conv4, i16* %kk16, align 2
--
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2016 Jul 27
2
Remove zext-unfolding from InstCombine
...InstCombine:
```
define signext i8 @foo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
entry:
%conv = sext i8 %a to i32
%and = and i32 %conv, 1
%cmp = icmp eq i32 %and, 0
%conv1 = zext i1 %cmp to i32
%conv2 = sext i8 %b to i32
%cmp3 = icmp eq i32 %conv2, 0
%conv4 = zext i1 %cmp3 to i32
%or = or i32 %conv1, %conv4
%conv5 = trunc i32 %or to i8
ret i8 %conv5
}
; Function Attrs: nounwind ssp uwtable
define signext i8 @goo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
entry:
%conv = sext i8 %a to i32
%and = and i32 %conv, 1...
2014 Oct 16
2
[LLVMdev] RFC: Should we have (something like) -extra-vectorizer-passes in -O2?
----- Original Message -----
> From: "Chandler Carruth" <chandlerc at google.com>
> To: "Zinovy Nis" <zinovy.nis at gmail.com>
> Cc: "Hal Finkel" <hfinkel at anl.gov>, "James Molloy" <james at jamesmolloy.co.uk>, "LLVM Developers Mailing List"
> <llvmdev at cs.uiuc.edu>
> Sent: Thursday, October 16, 2014
2012 Jul 16
0
[LLVMdev] !dbg metadata not generated for if.else->if.end branch
...100, %4, !dbg !51
%5 = load i32* %result, align 4, !dbg !51
%add3 = add nsw i32 %5, %sub, !dbg !51
store i32 %add3, i32* %result, align 4, !dbg !51
br label %if.end, !dbg !51
if.else: ; preds = %entry
%6 = load i8* %bar.addr, align 1, !dbg !52
%conv4 = sext i8 %6 to i32, !dbg !52
%sub5 = sub nsw i32 221, %conv4, !dbg !52
%7 = load i32* %result, align 4, !dbg !52
%add6 = add nsw i32 %7, %sub5, !dbg !52
store i32 %add6, i32* %result, align 4, !dbg !52
br label %if.end
if.end: ; preds = %if.else...
2012 Feb 17
0
[LLVMdev] Folding an insertelt chain
On Feb 17, 2012, at 12:50 AM, Ivan Llopard wrote:
> Hello,
>
> I've added a little combining operation in DAGCombiner to fold a chain of insertelt nodes if that chain is proved to fully overwrite the very first source vector. In which case, I supposed a build_vector is better. It seems to be safe but I don't know if it is correctly implemented or if it is already done somewhere
2012 Feb 17
3
[LLVMdev] Folding an insertelt chain
Hello,
I've added a little combining operation in DAGCombiner to fold a chain
of insertelt nodes if that chain is proved to fully overwrite the very
first source vector. In which case, I supposed a build_vector is better.
It seems to be safe but I don't know if it is correctly implemented or
if it is already done somewhere else. Please find attached the patch.
Regards,
Ivan
2009 Apr 20
4
[LLVMdev] Unnecessary moves after sign-extension in 2-address target
...et this IR:
define i32 @sext(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = trunc i32 %a to i8 ; <i8> [#uses=1]
%conv1 = sext i8 %conv to i32 ; <i32> [#uses=1]
%conv3 = trunc i32 %b to i16 ; <i16> [#uses=1]
%conv4 = sext i16 %conv3 to i32 ; <i32> [#uses=1]
%add = add i32 %conv1, %c ; <i32> [#uses=1]
%add6 = add i32 %add, %conv4 ; <i32> [#uses=1]
ret i32 %add6
}
And this not-so-great assembler code:
sext:
sextb r1
mov r4,r1 ### un...
2017 Feb 13
2
RFC: Representing unions in TBAA
...a !2
%add2 = add nsw i32 %add1, %3
%conv = sitofp i32 %add2 to float
%4 = load float, float* bitcast (%union.U* @u to float*), align 4, !tbaa
!11
%add3 = fadd float %conv, %4
%5 = load i32, i32* getelementptr inbounds (%struct.Q, %struct.Q* @q,
i32 0, i32 1, i32 0), align 4, !tbaa !2
%conv4 = sitofp i32 %5 to float
%add5 = fadd float %add3, %conv4
%6 = load float, float* bitcast (%union.U* getelementptr inbounds
(%struct.Q, %struct.Q* @q, i32 0, i32 1) to float*), align 4, !tbaa !11
%add6 = fadd float %add5, %6
%7 = load i32, i32* getelementptr inbounds (%struct.Q, %struct.Q*...
2015 Feb 04
2
[LLVMdev] Question on Machine Combiner Pass
...<ghoflehner at apple.com <mailto:ghoflehner at apple.com>
>
Date: Thu Aug 7 21:40:58 2014 +0000
MachineCombiner Pass for selecting faster instruction sequence on
AArch64
For this example code sequence:
%mul = mul nuw nsw i32 %conv2, %conv
%mul7 = mul nuw nsw i32 %conv6, %conv4
%add = add nuw nsw i32 %mul7, %mul
ret i32 %add
We generate the following assembly:
mul w8, w0, w1
mul w9, w2, w3
add w0, w9, w8
ret
Whereas I expected the MUL+ADD to be combined to MADD otherwise...
2016 Aug 04
2
Remove zext-unfolding from InstCombine
...o_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
> entry:
> %conv = sext i8 %a to i32
> %and = and i32 %conv, 1
> %cmp = icmp eq i32 %and, 0
> %conv1 = zext i1 %cmp to i32
> %conv2 = sext i8 %b to i32
> %cmp3 = icmp eq i32 %conv2, 0
> %conv4 = zext i1 %cmp3 to i32
> %or = or i32 %conv1, %conv4
> %conv5 = trunc i32 %or to i8
> ret i8 %conv5
> }
>
> ; Function Attrs: nounwind ssp uwtable
> define signext i8 @goo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
> entry:
> %conv =...
2016 Jul 21
2
Remove zext-unfolding from InstCombine
Hi all,
I have a question regarding a transformation that is carried out in InstCombine, which has been introduced by r48715. It unfolds expressions of the form `zext(or(icmp, (icmp)))` to `or(zext(icmp), zext(icmp)))` to expose pairs of `zext(icmp)`. In a subsequent iteration these `zext(icmp)` pairs could then (possibly) be optimized by another optimization (which has already been there before
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...r = getelementptr inbounds i16* %pe, i32 3
%0 = load i16* %add.ptr, align 2, !tbaa !5
%conv = zext i16 %0 to i32
%1 = shl nuw i32 %conv, 16
%sext = ashr i32 %1, 31
%. = trunc i32 %sext to i16
store i16 %., i16* %arraydecay, align 2
%and3 = and i32 %conv, 15
%or = or i32 %and3, 16
%conv4 = trunc i32 %or to i16
store i16 %conv4, i16* %incdec.ptr.1.i, align 2, !tbaa !5
%and7 = and i32 %conv, 32752
%cmp = icmp eq i32 %and7, 32752
br i1 %cmp, label %if.then11, label %if.end37
if.then11: ; preds = %entry
%and14 = and i16 %0, 15
%cmp15...