Displaying 6 results from an estimated 6 matches for "conv24".
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conv2
2013 Jan 21
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...<--- 16-bit comparison
%.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <--- 32-bit select
br label %if.end23, !dbg !511
if.end23: ; preds = %if.else, %for.body
%val1.0 = phi i32 [ 2047, %for.body ], [ %.conv, %if.else ]
%conv24 = trunc i32 %val1.0 to i16, !dbg !512
store i16 %conv24, i16* %arrayidx2, align 2, !dbg !512
The problem with this is that during instruction selection, the pair of comparison and select is no longer recognized as max operation because the operands of the two operations are not the same.
It se...
2013 Jan 21
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <---
> 32-bit select
> br label %if.end23, !dbg !511
>
> if.end23: ; preds = %if.else,
> %for.body
> %val1.0 = phi i32 [ 2047, %for.body ], [ %.conv, %if.else ]
> %conv24 = trunc i32 %val1.0 to i16, !dbg !512
> store i16 %conv24, i16* %arrayidx2, align 2, !dbg !512
>
> The problem with this is that during instruction selection, the pair of
> comparison and select is no longer recognized as max operation because the
> operands of the two operations a...
2013 Jan 21
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...> %.conv = select i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <--- 32-bit select
> br label %if.end23, !dbg !511
>
> if.end23: ; preds = %if.else, %for.body
> %val1.0 = phi i32 [ 2047, %for.body ], [ %.conv, %if.else ]
> %conv24 = trunc i32 %val1.0 to i16, !dbg !512
> store i16 %conv24, i16* %arrayidx2, align 2, !dbg !512
>
> The problem with this is that during instruction selection, the pair of comparison and select is no longer recognized as max operation because the operands of the two operations are not th...
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...ct i1 %cmp19, i32 -2048, i32 %conv, !dbg !511 <--- 32-bit select
>> br label %if.end23, !dbg !511
>>
>> if.end23: ; preds = %if.else, %for.body
>> %val1.0 = phi i32 [ 2047, %for.body ], [ %.conv, %if.else ]
>> %conv24 = trunc i32 %val1.0 to i16, !dbg !512
>> store i16 %conv24, i16* %arrayidx2, align 2, !dbg !512
>>
>> The problem with this is that during instruction selection, the pair of comparison and select is no longer recognized as max operation because the operands of the two operation...
2013 Jan 21
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...p19, i32 -2048, i32 %conv, !dbg !511
>> <--- 32-bit select
>> br label %if.end23, !dbg !511
>>
>> if.end23: ; preds = %if.else,
>> %for.body
>> %val1.0 = phi i32 [ 2047, %for.body ], [ %.conv, %if.else ]
>> %conv24 = trunc i32 %val1.0 to i16, !dbg !512
>> store i16 %conv24, i16* %arrayidx2, align 2, !dbg !512
>>
>> The problem with this is that during instruction selection, the pair of
>> comparison and select is no longer recognized as max operation because the
>> operands of...
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...4, %for.inc.6.i ], [ %35, %for.inc.7.i ], [ %36, %for.inc.8.i ], [ %37, %for.inc.9.i ]
%cmp10.i = icmp ugt i16 %.lcssa.i, %.lcssa23.i
br i1 %cmp10.i, label %if.then22, label %if.end36
if.then22: ; preds = %ecmpm.exit
%sub = add nsw i32 %conv.i, 65535
%conv24 = trunc i32 %sub to i16
call fastcc void @esubm(i16* %den, i16* %arraydecay18)
%49 = load i16* %arrayidx26.i, align 2, !tbaa !5
%50 = load i16* %add.ptr.i, align 2, !tbaa !5
%cmp4.i135 = icmp eq i16 %49, %50
br i1 %cmp4.i135, label %for.inc.i139, label %ecmpm.exit182
for.inc.i139:...