Displaying 20 results from an estimated 26 matches for "conv1".
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2015 Sep 30
2
InstCombine wrongful (?) optimization on BinOp with SameOperands
Hi all,
I have been looking at the way LLVM optimizes code before
forwarding it to the backend I develop for my company and while building
define i32 @test_extract_subreg_func(i32 %x, i32 %y) #0 {
entry:
%conv = zext i32 %x to i64
%conv1 = zext i32 %y to i64
%mul = mul nuw i64 %conv1, %conv
%shr = lshr i64 %mul, 32
%xor = xor i64 %shr, %mul
%conv2 = trunc i64 %xor to i32
ret i32 %conv2
}
I came upon the following optimization (during instcombine):
*IC: Visiting: %mul = mul nuw i64 %conv, %conv1
IC: Visiting: %sh...
2016 May 31
3
Signed Division and InstCombine
I was looking through the InstCombine pass, and I was wondering why signed
division is not considered a valid operation to combine in the
canEvaluateTruncated function. This means, given the following code:
%conv = sext i16 %0 to i32
%conv1 = sext i16 %1 to i32
%div = sdiv i32 %conv, %conv1
%conv2 = trunc i32 %div to i16
* Assume %0 and %1 are registers created from simple 16-bit loads.
We cannot reduce the sequence to:
%div = sdiv i16 %0 %1
What is the reason for the exclusion of sdiv from the operations considered
valid for execu...
2008 Sep 07
1
Request for advice on character set conversions (those damn Excel files, again ...)
...the following solution :
foo<-function(d, from="latin1",to="UTF-8"){
# Semi-smart conversion of a dataframe between charsets.
# Needed to ease use of those [@!] Excel files
# that have survived the Win3.1 --> Win95 --> NT transition,
# usually in poor shape..
conv1<-function(v,from,to) {
condconv<-function(v,from,to) {
cnv<-is.na(iconv(v,to,to))
v[cnv]<-iconv(v[cnv],from,to)
return(v)
}
if (is.factor(v)) {
l<-condconv(levels(v),from,to)
levels(v)<-l
return(v)
}
else if (is.character(v))...
2012 Dec 17
0
[LLVMdev] [PATCH] Teaching ScalarEvolution to handle IV=add(zext(trunc(IV)), Step)
...and i32 %result.03, 255
> 09: %add = add nsw i32 %conv2, 3
> 10: %inc = add nsw i32 %j.04, 1
> 11: %cmp = icmp slt i32 %inc, 8000
> 12: br i1 %cmp, label %for.body, label %for.end
> 13:
> 14: for.end: ; preds = %for.body
> 15: %conv1 = trunc i32 %add to i8
> 16: ret i8 %conv1
> 17: }
I'm confused about how you got this IR from that C testcase. What is
result_t? Did you do anything special?
> Unfortunately, the 'and' on line 8 prevents Scalar Evolution from
> being able to create an expression for ...
2018 Aug 06
2
Lowering ISD::TRUNCATE
...optnone
define dso_local zeroext i8 @Func(i8 zeroext %val1) #0 {
entry:
%val1.addr = alloca i8, align 1
store i8 %val1, i8* %val1.addr, align 1
%0 = load i8, i8* %val1.addr, align 1
%conv = zext i8 %0 to i16
%1 = load i8, i8* %val1.addr, align 1
%conv1 = zext i8 %1 to i16
%add = add nsw i16 %conv, %conv1
%conv2 = trunc i16 %add to i8
ret i8 %conv2
}
I looked into the X86 backend, which has a Z80-like register design,
i.e. being able to access the subregs AL (and AH) from AX directly,
without any specific truncation op...
2016 Jul 27
2
Remove zext-unfolding from InstCombine
...p, I examined the IR that clang generates for `foo` and `goo` just before they are passed to InstCombine:
```
define signext i8 @foo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
entry:
%conv = sext i8 %a to i32
%and = and i32 %conv, 1
%cmp = icmp eq i32 %and, 0
%conv1 = zext i1 %cmp to i32
%conv2 = sext i8 %b to i32
%cmp3 = icmp eq i32 %conv2, 0
%conv4 = zext i1 %cmp3 to i32
%or = or i32 %conv1, %conv4
%conv5 = trunc i32 %or to i8
ret i8 %conv5
}
; Function Attrs: nounwind ssp uwtable
define signext i8 @goo_before_InstCombine(i8 signext %a, i8 signe...
2012 Dec 10
3
[LLVMdev] [PATCH] Teaching ScalarEvolution to handle IV=add(zext(trunc(IV)), Step)
...[ %add, %for.body ]
08: %conv2 = and i32 %result.03, 255
09: %add = add nsw i32 %conv2, 3
10: %inc = add nsw i32 %j.04, 1
11: %cmp = icmp slt i32 %inc, 8000
12: br i1 %cmp, label %for.body, label %for.end
13:
14: for.end: ; preds = %for.body
15: %conv1 = trunc i32 %add to i8
16: ret i8 %conv1
17: }
Unfortunately, the 'and' on line 8 prevents Scalar Evolution from
being able to create an expression for '%add' that it knows how to
evaluate.
The patch detects this pattern in createNodeForPHI and creates an
equivalent expression t...
2008 May 02
1
Speedups with Ra and jit
...e might be interested in this little demo. For it I
used my machine, a 3-year old laptop with 2Gb memory running Windows
XP, and the good old convolution example, the same one as used on the
web page, (though the code on the web page has a slight glitch in it).
This is using Ra with R-2.7.0.
> conv1 <- function(a, b) {
> ### with Ra and jit
require(jit)
jit(1)
ab <- numeric(length(a)+length(b)-1)
for(i in 1:length(a))
for(j in 1:length(b))
ab[i+j-1] <- ab[i+j-1] + a[i]*b[j]
ab
}
>
> conv2 <- function(a, b) {
> ### w...
2015 Feb 04
6
[LLVMdev] llvm builtins
...}
; Function Attrs: nounwind readnone
declare float @powf(float, float) #1
; Function Attrs: nounwind uwtable
define void @fpowi() #0 {
entry:
%0 = load float* @f, align 4
%conv = fpext float %0 to double
%1 = load i32* @i, align 4
%2 = call double @llvm.powi.f64(double %conv, i32 %1)
%conv1 = fptrunc double %2 to float
store float %conv1, float* @fresult2, align 4
ret void
}
; Function Attrs: nounwind readnone
declare double @llvm.powi.f64(double, i32) #2
; Function Attrs: nounwind uwtable
define i32 @main() #0 {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval...
2012 Jul 16
0
[LLVMdev] !dbg metadata not generated for if.else->if.end branch
...2* %foo.addr, align 4, !dbg !49
%1 = load i8* %bar.addr, align 1, !dbg !49
%conv = sext i8 %1 to i32, !dbg !49
%add = add nsw i32 %0, %conv, !dbg !49
store i32 %add, i32* %result, align 4, !dbg !49
%2 = load i32* %foo.addr, align 4, !dbg !50
%3 = load i8* %bar.addr, align 1, !dbg !50
%conv1 = sext i8 %3 to i32, !dbg !50
%cmp = icmp sgt i32 %2, %conv1, !dbg !50
br i1 %cmp, label %if.then, label %if.else, !dbg !50
if.then: ; preds = %entry
%4 = load i32* %foo.addr, align 4, !dbg !51
%sub = sub nsw i32 100, %4, !dbg !51
%5 = load i32* %...
2012 Feb 17
0
[LLVMdev] Folding an insertelt chain
On Feb 17, 2012, at 12:50 AM, Ivan Llopard wrote:
> Hello,
>
> I've added a little combining operation in DAGCombiner to fold a chain of insertelt nodes if that chain is proved to fully overwrite the very first source vector. In which case, I supposed a build_vector is better. It seems to be safe but I don't know if it is correctly implemented or if it is already done somewhere
2011 Jul 11
1
Finding Confidence Intervals
...Clicks=c("500", "600"),
Conversions=c("100", "150"))
And here are the click through rates and conversion rates for each of the
headlines.
ctr1 = (500/1000)*100 # for headline 1
ctr2 = (600/1300)*100 # for headline 2
ctr1; ctr2
conv1 = (100/1000)*100 # for headline 1
conv2 = (150/1300)*100 # for headline 2
conv1; conv2
According to the sites above, I'm really interested in determining the
confidence intervals for the conversion rates for each headline. While 95%
confidence would be ideal, I'm really open to anything...
2012 Jun 27
2
[LLVMdev] 8-bit DIV IR irregularities
...ses an 8-bit unsigned divide. Why not use a 8-bit signed divide when using 8-bit signed values?
Here is the C code and IR:
char idiv8(char a, char b)
{
char c = a / b;
return c;
}
define signext i8 @idiv8(i8 signext %a, i8 signext %b) nounwind readnone {
entry:
%conv = sext i8 %a to i32
%conv1 = sext i8 %b to i32
%div = sdiv i32 %conv, %conv1
%conv2 = trunc i32 %div to i8
ret i8 %conv2
}
unsigned char div8(unsigned char a, unsigned char b)
{
unsigned char c = a / b;
return c;
}
define zeroext i8 @div8(i8 zeroext %a, i8 zeroext %b) nounwind readnone {
entry:
%div3 = udiv i8...
2012 Feb 17
3
[LLVMdev] Folding an insertelt chain
Hello,
I've added a little combining operation in DAGCombiner to fold a chain
of insertelt nodes if that chain is proved to fully overwrite the very
first source vector. In which case, I supposed a build_vector is better.
It seems to be safe but I don't know if it is correctly implemented or
if it is already done somewhere else. Please find attached the patch.
Regards,
Ivan
2014 May 23
2
[LLVMdev] clang -O2 versus opt -O2 | llc | clang
...6 %conv, i16* @b, align 2, !tbaa !6
store i16 1, i16* %0, align 2, !tbaa !6
%tobool = icmp eq i8 %dec, 0
br i1 %tobool, label %if.end, label %lbl
if.end: ; preds = %lbl
store i8 0, i8* @d, align 1, !tbaa !5
%2 = load i16* @a, align 2, !tbaa !6
%conv1 = sext i16 %2 to i32
ret i32 %conv1
}
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2009 Apr 20
4
[LLVMdev] Unnecessary moves after sign-extension in 2-address target
...s simple program:
int
sext (unsigned a, unsigned b, int c)
{
return (signed char) a + (signed short) b + c;
}
I get this IR:
define i32 @sext(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = trunc i32 %a to i8 ; <i8> [#uses=1]
%conv1 = sext i8 %conv to i32 ; <i32> [#uses=1]
%conv3 = trunc i32 %b to i16 ; <i16> [#uses=1]
%conv4 = sext i16 %conv3 to i32 ; <i32> [#uses=1]
%add = add i32 %conv1, %c ; <i32> [#uses=1]
%add6 = add i32 %add, %conv4...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...e operation on extracted elements rather than on the input
vectors themselves.
In the PR you linked, there is an example that shows the difference
(simplified to <2 x double> for brevity):
define dso_local <2 x double> @test(i64 %a, i64 %b) {
entry:
%conv = uitofp i64 %a to double
%conv1 = uitofp i64 %b to double
%vecinit = insertelement <2 x double> undef, double %conv, i32 0
%vecinit2 = insertelement <2 x double> %vecinit, double %conv1, i32 1
ret <2 x double> %vecinit2
}
The inputs here are scalars so I suppose it is quite possible (perhaps
likely) that...
2016 Aug 04
2
Remove zext-unfolding from InstCombine
...s for `foo` and `goo` just before they are passed to InstCombine:
>
> ```
> define signext i8 @foo_before_InstCombine(i8 signext %a, i8 signext %b) local_unnamed_addr #0 {
> entry:
> %conv = sext i8 %a to i32
> %and = and i32 %conv, 1
> %cmp = icmp eq i32 %and, 0
> %conv1 = zext i1 %cmp to i32
> %conv2 = sext i8 %b to i32
> %cmp3 = icmp eq i32 %conv2, 0
> %conv4 = zext i1 %cmp3 to i32
> %or = or i32 %conv1, %conv4
> %conv5 = trunc i32 %or to i8
> ret i8 %conv5
> }
>
> ; Function Attrs: nounwind ssp uwtable
> define signext...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...tors themselves.
>>
>> In the PR you linked, there is an example that shows the difference
>> (simplified to <2 x double> for brevity):
>> define dso_local <2 x double> @test(i64 %a, i64 %b) {
>> entry:
>> %conv = uitofp i64 %a to double
>> %conv1 = uitofp i64 %b to double
>> %vecinit = insertelement <2 x double> undef, double %conv, i32 0
>> %vecinit2 = insertelement <2 x double> %vecinit, double %conv1, i32 1
>> ret <2 x double> %vecinit2
>> }
>>
>> The inputs here are scalars so...
2012 Dec 18
2
[LLVMdev] [PATCH] Teaching ScalarEvolution to handle IV=add(zext(trunc(IV)), Step)
...> 09: %add = add nsw i32 %conv2, 3
>> 10: %inc = add nsw i32 %j.04, 1
>> 11: %cmp = icmp slt i32 %inc, 8000
>> 12: br i1 %cmp, label %for.body, label %for.end
>> 13:
>> 14: for.end: ; preds = %for.body
>> 15: %conv1 = trunc i32 %add to i8
>> 16: ret i8 %conv1
>> 17: }
> I'm confused about how you got this IR from that C testcase. What is
> result_t? Did you do anything special?
Sorry, result_t is signed char. I was experimenting with other result
types and mistakenly copied an interme...