search for: constantstepvector

Displaying 3 results from an estimated 3 matches for "constantstepvector".

2018 Jun 05
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...used for constant folding. Our downstream >> compiler (using Constants instead of intrinsics) relies quite heavily on this >> for good code generation, so we will need to find new ways to recognize and >> fold these values. > > As above, we could add ConstantVScale and also ConstantStepVector (or > ConstantIota). They won't fold to compile-time values but the > expressions could be simplified. I haven't really thought through the > implications of this, just brainstorming ideas. What does your > downstream compiler require in terms of constant support. What kinds...
2018 Jun 06
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...tant. > > Ultimately whatever is easier for LLVM to analyze in the long run is > best. Intrinsics often block optimization. I don't know whether vscale > would be "eaiser" as a Constant or an Instruction. > >>> As above, we could add ConstantVScale and also ConstantStepVector (or >>> ConstantIota). They won't fold to compile-time values but the >>> expressions could be simplified. I haven't really thought through the >>> implications of this, just brainstorming ideas. What does your >>> downstream compiler require in terms...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on