search for: constantsdnod

...getOperand(1); // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) - if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && - RHSShift.getOperand(1).getOpcode() == ISD::Constant) { - uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); - uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); + if (LHSShiftAmt.getOpcode() == ISD::Constant && + RHSShiftAmt.getOpcode() == ISD::Constant) { + uint64_t LShVal = cast<ConstantSDNode>(LHSS...

...erimenting with a number of approaches to representation in > SDAG, and I have found one that seems to work best, and would be the least > intrusive (unfortunately most approaches to this problem are somewhat > intrusive). > > Specifically, I want to: > 1) move most of the body of ConstantSDNode to a new class, > ConstantIntSDNode, which would derives from ConstantSDNode. ConstantSDNode > would act as the base class for immediates-post-static-linking. Change > most references to ConstantSDNode in C++ code to refer to > ConstantIntSDNode. However, "imm" in tblgen code...

...of approaches to representation in >> SDAG, and I have found one that seems to work best, and would be the least >> intrusive (unfortunately most approaches to this problem are somewhat >> intrusive). >> >> Specifically, I want to: >> 1) move most of the body of ConstantSDNode to a new class, >> ConstantIntSDNode, which would derives from ConstantSDNode. ConstantSDNode >> would act as the base class for immediates-post-static-linking. Change >> most references to ConstantSDNode in C++ code to refer to >> ConstantIntSDNode. However, "imm&quot...

...ial situation when the is_stmt field in the DWARF line table should be used? If we set is_stmt=0 for the instruction loading the constant, then a debugger can choose not to stop on that instruction when doing "step" on source level. That way we can keep the original source location for a ConstantSDNode, but also telling the debugger that this isn't a recommended breakpoint location for that line. Using is_stmt=0 is ofcourse only interesting if the constant load I hoisted so that it isn't adjacent to other is_stmt=1 instructions on the same line. /Björn From: llvm-dev <llvm-dev-bounc...

...separately. I have been experimenting with a number of approaches to representation in SDAG, and I have found one that seems to work best, and would be the least intrusive (unfortunately most approaches to this problem are somewhat intrusive). Specifically, I want to: 1) move most of the body of ConstantSDNode to a new class, ConstantIntSDNode, which would derives from ConstantSDNode. ConstantSDNode would act as the base class for immediates-post-static-linking. Change most references to ConstantSDNode in C++ code to refer to ConstantIntSDNode. However, "imm" in tblgen code would continue to m...

...RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) { op3 = cast<RegisterSDNode>(Reg3)->getReg(); fprintf(stderr,"Op3 is register and regnum is %d\n",op3); } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Reg3)) { op3 = C->getZExtValue(); fprintf(stderr,"Op3 is constant and value is %d\n",op3); } When I run this code Reg3 is found out to be a ConstantSDNode but i...

...n advice > from you. r174746 is specifically related to pre-increment loads and stores. I think that the first step is to narrow down the problematic case. In DAGCombiner::CombineToPreIndexedLoadStore, there is a loop which starts with: SmallVector<SDNode *, 16> OtherUses; if (isa<ConstantSDNode>(Offset)) for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(), E = BasePtr.getNode()->use_end(); I != E; ++I) { SDNode *Use = *I; 1. Make the loop skip cases where Use->getOpcode() == ISD::ADD and then Use->getOpcode() == ISD::SUB and try to figure out w...

Hello Hal, I have a strong suspicion that your constant folding optimization introduced at r174746 is broken on ARM. There is a bug about it: http://llvm.org/bugs/show_bug.cgi?id=15581 There is no such issue with 3.2, and reverting r174746 on top of r178740 also fixes the problem. I'm trying to fix it myself, but still have no good ideas; so it would be great to have an advice from you.

...avior given Swift code that looks like this: 1| var input = [16, 14, 10, 9, 8, 7, 4, 3, 2, 1] //< Only number 1 is relevant. 2| print("start") TL;DR: The debugger steps from line 2 -> 1 -> 2 in this code example. One clean way to fix this bug is to remove debug locations from ConstantSDNodes, and I'm asking if there are any objections to doing that. In more detail: The problem appears to be that we assign a debug location to the ConstantSDNode for "1". When this constant is used again (as it happens to be in the lowered version of the call to print()) the debugger ste...

...nkel wrote: > Looking briefly at the code in comment 5 of PR15581, is that the pre-decrement case? > I can't test that case on PPC, so I can certainly believe that there is a problem somewhere. > The relevant code is a little farther down: > > APInt OV = > cast<ConstantSDNode>(Offset)->getAPIntValue(); > if (AM == ISD::PRE_DEC) > OV = -OV; > > ConstantSDNode *CN = > cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); > APInt CNV = CN->getAPIntValue(); > if (OtherUses[i]->getOpcode() == I...

...ast<RegisterSDNode>(Reg3)) > { > op3 = cast<RegisterSDNode>(Reg3)->getReg(); > fprintf(stderr,"Op3 is register and regnum is %d\n",op3); > } > else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Reg3)) > { > op3 = C->getZExtValue(); > fprintf(stderr,"Op3 is constant and value is %d\n",op3); > } > > When I run this code...

...really wanted the line table entry for line 2 to include the constant materialization code for some VS debugger feature. Got it. (For others following along, there's more discussion about this debugger feature in the commit description for r327581.) > I think if you remove locations from ConstantSDNodes, you might want to add a late pass that propagates source locations backwards onto location-less instructions. This would also avoid some special cases when a basic block starts with an instruction that lacks location information. See CodeViewDebug::beginInstruction and DwarfDebug::beginInstructi...

...de generation. Does anyone have any insight in to what the problem might be or how to go about debugging it? Regards, Ryan llc: /home/lefever/work/llvm-cvs-070325/include/llvm/Support/Casting.h:199: typename llvm::cast_retty<To, From>::ret_type llvm::cast(const Y&) [with X = llvm::ConstantSDNode, Y = llvm::SDOperand]: Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed. /home/lefever/work/install/bin/llc((anonymous namespace)::PrintStackTrace()+0x1a)[0x88b77e6] /home/lefever/work/install/bin/llc((anonymous namespace)::SignalHa...

...)) > > { > > op3 = cast<RegisterSDNode>(Reg3)->getReg(); > > fprintf(stderr,"Op3 is register and regnum is > %d\n",op3); > > } > > else if (ConstantSDNode *C = > dyn_cast<ConstantSDNode>(Reg3)) > > { > > op3 = C->getZExtValue(); > > fprintf(stderr,"Op3 is constant and value is > %d\n",op3); > > } > > > &gt...

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

...stack trace and then create a PR for this problem. Thanks, Reid. > > Regards, > Ryan > > llc: > /home/lefever/work/llvm-cvs-070325/include/llvm/Support/Casting.h:199: > typename llvm::cast_retty<To, From>::ret_type llvm::cast(const Y&) [with > X = llvm::ConstantSDNode, Y = llvm::SDOperand]: Assertion `isa<X>(Val) > && "cast<Ty>() argument of incompatible type!"' failed. > /home/lefever/work/install/bin/llc((anonymous > namespace)::PrintStackTrace()+0x1a)[0x88b77e6] > /home/lefever/work/install/bin/llc((anonymous...

...not a complete lie. > --paulr >   <> > From: vsk at apple.com [mailto:vsk at apple.com] > Sent: Wednesday, June 20, 2018 1:48 PM > To: Reid Kleckner > Cc: Robinson, Paul; llvm-dev; Justin Bogner; David Li; David Blaikie > Subject: Re: [RFC] Removing debug locations from ConstantSDNodes > > On Jun 19, 2018, at 6:36 PM, Reid Kleckner <rnk at google.com <mailto:rnk at google.com>> wrote: > > On Tue, Jun 19, 2018 at 5:46 PM Vedant Kumar <vsk at apple.com <mailto:vsk at apple.com>> wrote: > Someone (Reid?) mentioned that we could try sinkin...

...problem. > > Thanks, > > Reid. > > >>Regards, >>Ryan >> >>llc: >>/home/lefever/work/llvm-cvs-070325/include/llvm/Support/Casting.h:199: >>typename llvm::cast_retty<To, From>::ret_type llvm::cast(const Y&) [with >>X = llvm::ConstantSDNode, Y = llvm::SDOperand]: Assertion `isa<X>(Val) >>&& "cast<Ty>() argument of incompatible type!"' failed. >>/home/lefever/work/install/bin/llc((anonymous >>namespace)::PrintStackTrace()+0x1a)[0x88b77e6] >>/home/lefever/work/install/bin/llc(...

...lues() && "Lowering call/formal_arguments produced unexpected # results!"' failed. This is what my LowerCALL looks like: SDOperand MCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; assert(!isVarArg); bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; SDOperand Callee = Op.getOperand(4); MVT::ValueType RetVT= Op.Val->getValueType(0); unsigned NumOps = (Op.getNumOperan...

...dering, since a release is planned, how aware anyone was of these warnings under VS and whether I should spend some time to help clean them up? Or just leave them as is. Here is a typical examples: warning C4244: '+=' : conversion from 'uint64_t' to 'unsigned int' if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) { Wayne