Displaying 5 results from an estimated 5 matches for "conher".
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conter
2013 May 09
4
[LLVMdev] Predicated Vector Operations
...Ptr, <false, true>)
> ...
>
> Assuming there is no specific synchronization relevant to Ptr between
> these two threads and their masked stores, does this form a data race
> or not?
It entirely depends on the hardware implementation. In most cases I
would say yes due to cache conherence issues. From a purely theoretical
machine that doesn't have false sharing, there would be no data race.
Of course this assumes that thread B won't access the element stored by
thread A and vice versa.
> From a memory model perspective, if this does *not* form a data race,
> tha...
2013 May 09
0
[LLVMdev] Predicated Vector Operations
On Thu, May 9, 2013 at 1:09 AM, Nadav Rotem <nrotem at apple.com> wrote:
> On May 8, 2013, at 4:00 PM, Eric Christopher <echristo at gmail.com> wrote:
>
>
> Thinking that a masked store is conservatively a store of the full
> width of the store right?
>
>
> It depends on the optimization. Consider this example:
>
> masked_store(Val, Ptr , M)
> X =
2013 May 09
0
[LLVMdev] Predicated Vector Operations
...> >
> > Assuming there is no specific synchronization relevant to Ptr between
> > these two threads and their masked stores, does this form a data race
> > or not?
>
> It entirely depends on the hardware implementation. In most cases I
> would say yes due to cache conherence issues. From a purely theoretical
> machine that doesn't have false sharing, there would be no data race.
>
> Of course this assumes that thread B won't access the element stored by
> thread A and vice versa.
>
> > From a memory model perspective, if this does *not...
2013 May 08
4
[LLVMdev] Predicated Vector Operations
On May 8, 2013, at 4:00 PM, Eric Christopher <echristo at gmail.com> wrote:
>
> Thinking that a masked store is conservatively a store of the full
> width of the store right?
It depends on the optimization. Consider this example:
masked_store(Val, Ptr , M)
X = masked_load(Ptr, M2)
If you assume that your store actually overwrites everything in that memory location then you
2013 May 12
0
[LLVMdev] Predicated Vector Operations
...e to not look for a reasonable target independent
abstraction which we can teach the middle-end optimizers about (even if it
does take the form of intrinsics). Maybe there is no such abstraction? That
in and of itself would be surprising to me.
> In most cases I
> would say yes due to cache conherence issues. From a purely theoretical
> machine that doesn't have false sharing, there would be no data race.
>
I think you're trying to reason about this from a hardware perspective, and
I'm trying to talk about what the right theoretical model for the memory
model is... While...