search for: config_pci_mmconfig

From: Otavio Pontes <otavio.pontes at intel.com> Use the PCI mmconfig base address exported by jailhouse in boot parameters in order to access the memory mapped PCI configuration space. Signed-off-by: Otavio Pontes <otavio.pontes at intel.com> [Jan: rebased, fixed !CONFIG_PCI_MMCONFIG] Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> --- arch/x86/include/asm/pci_x86.h | 2 ++ arch/x86/kernel/jailhouse.c | 7 +++++++ arch/x86/pci/mmconfig-shared.c | 4 ++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/inc...

From: Otavio Pontes <otavio.pontes at intel.com> Use the PCI mmconfig base address exported by jailhouse in boot parameters in order to access the memory mapped PCI configuration space. Signed-off-by: Otavio Pontes <otavio.pontes at intel.com> [Jan: rebased, fixed !CONFIG_PCI_MMCONFIG] Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> --- arch/x86/include/asm/pci_x86.h | 2 ++ arch/x86/kernel/jailhouse.c | 7 +++++++ arch/x86/pci/mmconfig-shared.c | 4 ++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/inc...

From: Otavio Pontes <otavio.pontes at intel.com> Use the PCI mmconfig base address exported by jailhouse in boot parameters in order to access the memory mapped PCI configuration space. Signed-off-by: Otavio Pontes <otavio.pontes at intel.com> [Jan: rebased, fixed !CONFIG_PCI_MMCONFIG] Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> --- arch/x86/include/asm/pci_x86.h | 2 ++ arch/x86/kernel/jailhouse.c | 7 +++++++ arch/x86/pci/mmconfig-shared.c | 4 ++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/inc...

...memory mapped PCI configuration space. > --- a/arch/x86/kernel/jailhouse.c > +++ b/arch/x86/kernel/jailhouse.c > @@ -124,6 +124,13 @@ static int __init jailhouse_pci_arch_init(void) > if (pcibios_last_bus < 0) > pcibios_last_bus = 0xff; > > +#ifdef CONFIG_PCI_MMCONFIG > + if (setup_data.pci_mmconfig_base) { > + pci_mmconfig_add(0, 0, 0xff, setup_data.pci_mmconfig_base); Hmm... Shouldn't be pcibios_last_bus instead of 0xff? > + pci_mmcfg_arch_init(); > + } > +#endif -- With Best Regards, Andy Shevche...

From: Otavio Pontes <otavio.pontes at intel.com> Use the PCI mmconfig base address exported by jailhouse in boot parameters in order to access the memory mapped PCI configuration space. Signed-off-by: Otavio Pontes <otavio.pontes at intel.com> [Jan: rebased, fixed !CONFIG_PCI_MMCONFIG, used pcibios_last_bus] Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> --- arch/x86/include/asm/pci_x86.h | 2 ++ arch/x86/kernel/jailhouse.c | 8 ++++++++ arch/x86/pci/mmconfig-shared.c | 4 ++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/...

I thought I''d pass along a few tips for getting the Intel DQ35JO motherboard to play nice with Xen: 1. The dom0 kernel won''t boot with CONFIG_PCI_MMCONFIG enabled. If you get a hang during boot after seeing this message: ACPI: PCI Root Bridge [PCI0] (0000:00) ...then MMCONFIG is your problem. Some kernels seem to support a pci=nommconfig option, but my Gentoo 2.6.21 Xen kernel didn''t. The solution was to build the kernel without MMCO...

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

...arch/x86/kernel/Makefile index aed9296dccd3..b2c9e230e2fe 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -143,6 +143,6 @@ ifeq ($(CONFIG_X86_64),y) obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o + obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o obj-y += vsmp_64.o endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index ea831c858195..47edf599f6fd 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -690,7 +690,7 @@ st...

...arch/x86/kernel/Makefile index 29786c87e864..73ccf80c09a2 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y) obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o + obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o obj-y += vsmp_64.o endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f0e6456ca7d3..12bc0a1139da 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -716,7 +716,7 @@ st...

...arch/x86/kernel/Makefile index 29786c87e864..73ccf80c09a2 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y) obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o + obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o obj-y += vsmp_64.o endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f0e6456ca7d3..12bc0a1139da 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -716,7 +716,7 @@ st...

...arch/x86/kernel/Makefile index 29786c87e864..73ccf80c09a2 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y) obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o + obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o obj-y += vsmp_64.o endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f0e6456ca7d3..12bc0a1139da 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -716,7 +716,7 @@ st...

...arch/x86/kernel/Makefile index 29786c87e864..73ccf80c09a2 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y) obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o + obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o obj-y += vsmp_64.o endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f0e6456ca7d3..12bc0a1139da 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -716,7 +716,7 @@ st...

....5. The info I need to start with is the following: 1) Is PCIe Advanced Error Reporting (including error injections) known to work in 5.5? 2) What configuration options do I need to select in order to enable it? I'm using the following configs: CONFIG_ACPI=y CONFIG_PCI=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCIEPORTBUS=y CONFIG_PCIEAER=y CONFIG_PCIE_ECRC=y CONFIG_PCIE_AER_INJECT=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_MSI=y I also have the kernel boot parameter aerdriver.forceload=y With this config, I see that the relevant devices appear to support Advanced Error Reporting (visible in lspci -v o...

...mmconfig space is accessed thousands times, one after another; that causes fixed map & unmap continuously very fast for a long time. Currently the fix-mapped virtual address for Shared_info_page for dom0 & the PCI mmconfig page are adjacent in the fixed_addresses in the fixedmap.h. #ifdef CONFIG_PCI_MMCONFIG FIX_PCIE_MCFG, #endif FIX_SHARED_INFO, FIX_GNTTAB_BEGIN, I am suspecting that this is causing a race condition because of writable page tables. While accessing the PCI mmconfig on i386 the dom0 kernel (cpu 0) is continuously rewriting into the pte for FIX_PCIE_MCFG at a very fast ra...