search for: config_iommu_api

If CONFIG_IOMMU_API is n, build fails: vers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c:37:9: error: implicit declaration of function dev_iommu_fwspec_get; did you mean iommu_fwspec_free? [-Werror=implicit-function-declaration] spec = dev_iommu_fwspec_get(device->dev); ^~~~~~~~~~~~~~~~~~~~ iommu_fw...

...tio-iommu.c (100%) diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 11f1771104f3..fc7523042512 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += amd/ intel/ arm/ +obj-y += amd/ intel/ arm/ virtio/ obj-$(CONFIG_IOMMU_API) += iommu.o obj-$(CONFIG_IOMMU_API) += iommu-traces.o obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o @@ -26,4 +26,3 @@ obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o obj-$(CONFIG_S390_IOMMU) += s390-iommu.o obj-$(CONFIG_HYPERV_IOMMU) += hyperv-iom...

...b45a186..2f34c5a 100644 --- a/lib/include/nvif/os.h +++ b/lib/include/nvif/os.h @@ -124,6 +124,12 @@ typedef dma_addr_t resource_size_t; #define __printf(a,b) #define __user +#if defined(CONFIG_ARM) +#define IS_ENABLED_CONFIG_ARM 1 +#else +#define IS_ENABLED_CONFIG_ARM 0 +#endif + #if defined(CONFIG_IOMMU_API) #define IS_ENABLED_CONFIG_IOMMU_API 1 #else -- 2.10.0

...RE. > > + * > > + * Authors: Thierry Reding > > + */ > > + > > +#include "priv.h" > > + > > +static void > > +gp10b_ltc_init(struct nvkm_ltc *ltc) > > +{ > > + struct nvkm_device *device = ltc->subdev.device; > > +#ifdef CONFIG_IOMMU_API > > + struct iommu_fwspec *spec; > > +#endif > > + > > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); > > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr); > > + nvkm_wr32(device, 0x100800, ltc->ltc_nr); > > + > > +#ifdef CONFIG_IOMMU_API > > +...

...rry Reding > > > + */ > > > + > > > +#include "priv.h" > > > + > > > +static void > > > +gp10b_ltc_init(struct nvkm_ltc *ltc) > > > +{ > > > + struct nvkm_device *device = ltc->subdev.device; > > > +#ifdef CONFIG_IOMMU_API > > > + struct iommu_fwspec *spec; > > > +#endif > > > + > > > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); > > > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr); > > > + nvkm_wr32(device, 0x100800, ltc->ltc_nr); > > > + > > &g...

...is device may present to the IOMMU + */ +struct iommu_fwspec { + const struct iommu_ops *ops; + struct fwnode_handle *iommu_fwnode; + void *iommu_priv; + u32 flags; + unsigned int num_ids; + u32 ids[1]; +}; + +/* ATS is supported */ +#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) + #ifdef CONFIG_IOMMU_API /** @@ -565,27 +586,6 @@ extern struct iommu_group *generic_device_group(struct device *dev); /* FSL-MC device grouping function */ struct iommu_group *fsl_mc_device_group(struct device *dev); -/** - * struct iommu_fwspec - per-device IOMMU instance data - * @ops: ops for this device's I...

...+++ b/lib/include/nvif/os.h > @@ -124,6 +124,12 @@ typedef dma_addr_t resource_size_t; > #define __printf(a,b) > #define __user > > +#if defined(CONFIG_ARM) > +#define IS_ENABLED_CONFIG_ARM 1 > +#else > +#define IS_ENABLED_CONFIG_ARM 0 > +#endif > + > #if defined(CONFIG_IOMMU_API) > #define IS_ENABLED_CONFIG_IOMMU_API 1 > #else > -- > 2.10.0 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

From: Thierry Reding <treding at nvidia.com> The nouveau_fence_get_get_driver_name() function has a redundant _get in its name. Remove it. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_fence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c

...straightforward, except for the arm-smmu (_not_ arm-smmu-v3) and the qcom iommu driver. Unfortunatly I don't have the hardware for those, so any testing of these drivers is greatly appreciated. Please review. Regards, Joerg Changes to v1: - Rebased to v5.6-rc5 - Fixed compile error with CONFIG_IOMMU_API=n - Added Jean-Philippes fix to the ACPI/IORT patch Joerg Roedel (15): iommu: Define dev_iommu_fwspec_get() for !CONFIG_IOMMU_API ACPI/IORT: Remove direct access of dev->iommu_fwspec drm/msm/mdp5: Remove direct access of dev->iommu_fwspec iommu/tegra-gart: Remove direct access of de...

...a53aa8f45 100644 --- a/lib/include/nvif/os.h +++ b/lib/include/nvif/os.h @@ -130,12 +130,6 @@ typedef dma_addr_t resource_size_t; #define IS_ENABLED_CONFIG_ARM 0 #endif -#if defined(CONFIG_ARM64) -#define IS_ENABLED_CONFIG_ARM64 1 -#else -#define IS_ENABLED_CONFIG_ARM64 0 -#endif - #if defined(CONFIG_IOMMU_API) #define IS_ENABLED_CONFIG_IOMMU_API 1 #else -- 2.8.3

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will

...f_bool y select ARM_HAS_SG_CHAIN select NEED_SG_DMA_LENGTH diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h index 3234fe9bba6e..c3cf38e16866 100644 --- a/arch/arm/include/asm/device.h +++ b/arch/arm/include/asm/device.h @@ -13,9 +13,7 @@ struct dev_archdata { #ifdef CONFIG_IOMMU_API void *iommu; /* private IOMMU data */ #endif -#ifdef CONFIG_ARM_DMA_USE_IOMMU struct dma_iommu_mapping *mapping; -#endif #ifdef CONFIG_XEN const struct dma_map_ops *dev_dma_ops; #endif @@ -31,10 +29,6 @@ struct pdev_archdata { #endif }; -#ifdef CONFIG_ARM_DMA_USE_IOMMU #define to_dma_...

...nclude/nvif/os.h > @@ -130,12 +130,6 @@ typedef dma_addr_t resource_size_t; > #define IS_ENABLED_CONFIG_ARM 0 > #endif > > -#if defined(CONFIG_ARM64) > -#define IS_ENABLED_CONFIG_ARM64 1 > -#else > -#define IS_ENABLED_CONFIG_ARM64 0 > -#endif > - > #if defined(CONFIG_IOMMU_API) > #define IS_ENABLED_CONFIG_IOMMU_API 1 > #else >

TTM-allocated coherent objects were populated using the DMA API and accessed using the mapping it returned to workaround coherency issues. These issues seem to have been solved, thus remove this extra case to handle and use the regular kernel mapping functions. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nouveau_bo.c | 61

...,6 +124,12 @@ typedef dma_addr_t resource_size_t; >> #define __printf(a,b) >> #define __user >> >> +#if defined(CONFIG_ARM) >> +#define IS_ENABLED_CONFIG_ARM 1 >> +#else >> +#define IS_ENABLED_CONFIG_ARM 0 >> +#endif >> + >> #if defined(CONFIG_IOMMU_API) >> #define IS_ENABLED_CONFIG_IOMMU_API 1 >> #else >> -- >> 2.10.0 >> >> _______________________________________________ >> Nouveau mailing list >> Nouveau at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/nouveau >...

Here are a few small fixes for issues we found while implementing support for GM20B. The first two are specific to Tegra/GK20A, but the last 3 patches may have a broader (hopefully beneficial) effect. Note that the newly introduced gf100_gr_wait_idle() function on patch 5/5 is exported on purpose. GK20A and GM20B drivers will soon make use of it. Ben, since you seemed to like these changes, a

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

...CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_IRQ_PER_CPU=y +# CONFIG_IOMMU_API is not set diff --git a/arch/ia64/xen/Kconfig b/arch/ia64/xen/Kconfig index f1683a2..515e082 100644 --- a/arch/ia64/xen/Kconfig +++ b/arch/ia64/xen/Kconfig @@ -8,8 +8,7 @@ config XEN depends on PARAVIRT && MCKINLEY && IA64_PAGE_SIZE_16KB && EXPERIMENTAL select XEN_XENCOM...