Displaying 13 results from an estimated 13 matches for "conditionalise".
2017 Mar 17
3
LoopVectorizer with ifconversion
...rote:
> In general, this is true everywhere. In a large vectorized loop, this cost
> may well be worthwhile. The idea is that the cost model should account for
> all of these costs. If it doesn't properly, we should fix that.
Isn't this only worth when the SIMD instructions can be
conditionalised per lane? I believe AVX512 and SVE have such
abilities, but not NEON or SSE.
Does SystemZ support conditionalisation in SIMD?
cheers,
--renato
2014 May 09
4
[LLVMdev] ARM64 -> AArch64 merge status
...and all known bugs are fixed upstream.
This includes NEON instruction selection.
§ I’m still running testing to validate, but this can be thought of as
complete.
o [DONE] Support for no fpu/no neon/ no crc
o [DONE] A53 scheduler
o [DONE] Inline assembly
o [DONE] Predefines
o [DONE] Conditionalise cyclone/Darwin
§ Only the “LDR q” -> “LDP d, d” splitting pass to really conditionalise –
only benchmarks will really show though.
o [?] ADRP CSE
§ This optimization, being worked on by Jiangning, has been half ported to
ARM64. But it hasn’t been committed to AArch64 yet, so it can’t be
c...
2011 Oct 17
1
[LLVMdev] Optimization for size
Hi,
Looking at bugzilla PR11087, I'd like to conditionalise a transformation in
ARMIselLowering.cpp based on whether we're compiling for codesize or
performance.
-Os doesn't actually exist for llc, and I can't see an obvious place where
that condition would be set. Where do we specify if we're optimizing for
codesize or performance?...
2011 Oct 17
1
[LLVMdev] Optimization for size
On Mon, Oct 17, 2011 at 7:58 AM, James Molloy <james.molloy at arm.com> wrote:
> Hi,
>
>
>
> Looking at bugzilla PR11087, I’d like to conditionalise a transformation in
> ARMIselLowering.cpp based on whether we’re compiling for codesize or
> performance.
>
>
>
> -Os doesn’t actually exist for llc, and I can’t see an obvious place where
> that condition would be set. Where do we specify if we’re optimizing for
> codesize...
2017 Mar 17
2
LoopVectorizer with ifconversion
Hi,
it seems to be generally a bad idea to enable vectorization of
conditional stores on SystemZ, because it will cost extra instructions
both to 1. extract compare result element 2. Do a test-under-mask
instruction on that element 3. conditional branch past the store block.
Ideally, I would like to adjust the cost for the vector compare. I am
not sure if this is feasable since I would need
2003 Oct 07
1
[Bug 631] Build fails on Redhat Linux 6.x
http://bugzilla.mindrot.org/show_bug.cgi?id=631
dtucker at zip.com.au changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |patch
------- Additional Comments From dtucker at zip.com.au 2003-10-07 18:23 -------
Is that specfile patch OK or is there a better
2024 Apr 26
2
queries for a set of values
...nt because it needs
to allocate for each node in the tree).
One difference is that filter here will match everything if there are
no filter terms, so you can just always apply it:
query = Xapian::Query(OP_FILTER, query, filter);
The notmuch way will match nothing for that case so you need to
conditionalise applying the filter (assuming you still want to match
something when there are no filter terms).
> With a set of integers I have (after sortable_serialise), would the
> best way be to OP_OR a bunch of OP_VALUE_RANGE queries together?
>
> So, perhaps something like:
>
> Query(O...
2024 Apr 26
1
queries for a set of values
I probably should've used boolean terms in addition to numeric
values when indexing, but currently I have a set of numeric
values[1] and trying to avoid having to reindex ~250GB DBs
(and asking numerous users to do the same).
Say I have a bunch of values which I want to filter a query against.
If I had boolean terms, it could just OP_OR against the whole set.
IOW, this is what notmuch does
2013 Sep 13
10
[PATCH RFC 0/8] xen/arm: initial cubieboard2 support.
See http://www.gossamer-threads.com/lists/xen/devel/297170 for some
information on how to get this going.
I''ve rebased and addressed the review comments.
As before several of the patches are not to be applied because they can
be done better using infrastructure from Julien''s "Allow Xen to boot
with a raw Device Tree" patch. They are included for completeness.
With
1999 May 12
1
Memory crash. (PR#194)
I just had a memory crash with R-0.64.1.
I am running under intel pentium 200mhz under slackware linux 2.0.30.
1/home/plindsey >gdb /usr/local/src/R/bin/R.binary core
GDB is free software and you are welcome to distribute copies of it
under certain conditions; type "show copying" to see the conditions.
There is absolutely no warranty for GDB; type "show warranty" for
2015 Oct 12
13
[Bug 2478] New: Escape sequences (starting with ~) don't work when remote shell is BusyBox ash
https://bugzilla.mindrot.org/show_bug.cgi?id=2478
Bug ID: 2478
Summary: Escape sequences (starting with ~) don't work when
remote shell is BusyBox ash
Product: Portable OpenSSH
Version: 7.1p1
Hardware: ix86
OS: Linux
Status: NEW
Severity: minor
Priority: P5
2013 Sep 20
20
[PATCH v3 0/7] support for cubieboard2 / sunxi processors
See http://www.gossamer-threads.com/lists/xen/devel/297170 for some
information on how to get this going.
I''ve rebased and addressed the review comments.
With this rebase I''ve picked up some patches from Julien which were
required to do things properly, so the gic v7 and device blacklisting
patches have been changed to use the proper mechanisms.
Previously I was able to boot
2016 Sep 21
5
RFC: Extending LV to vectorize outerloops
Proposal for extending the Loop Vectorizer to handle Outer Loops
================================================================
Goal:
-----
We propose to extend the innermost Loop Vectorizer to also handle outerloops (cf.[1]). Our aim is to best leverage the efforts already invested in the existing innermost Loop Vectorizer rather than introduce a separate pass dedicated to outerloop