search for: condcodesdnode

...VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.getSizeInBits() crashes, because TLI.getSetCCResultType returns an invalid MVT type and LLVMTy is NULL. Since there is no way to specify the LLVMTy manually, there is no way to fix this without finding all of the locations that use this and disabling them. I&...

...VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.getSizeInBits() crashes, because TLI.getSetCCResultType returns an invalid MVT type and LLVMTy is NULL. Since there is no way to specify the LLVMTy manually, there is no way to fix this without finding all of the locations that use this and disabling them. I&...

...VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.getSizeInBits() crashes, because TLI.getSetCCResultType returns an invalid MVT type and LLVMTy is NULL. Since there is no way to specify the LLVMTy manually, there is no way to fix this without finding all of the locations that use this and disabling them. I&...

...VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.getSizeInBits() crashes, because TLI.getSetCCResultType returns an invalid MVT type and LLVMTy is NULL. Since there is no way to specify the LLVMTy manually, there is no way to fix this without finding all of the locations that use this and disabling them. I&...

...isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); } and the AND is then dropped by TargetLowering::SimplifyDemandedBits ... switch (Op...

...bitsLE(N0.getValueType())) { > bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ > (N1C->getAPIntValue() != 1); > if (TrueWhenTrue) > return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); > > // Invert the condition. > ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); > CC = ISD::getSetCCInverse(CC, > > N0.getOperand(0).getValueType().isInteger()); > return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), > CC); > } > > > and the AND is then dropped by > > Target...

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...etTypeToTransformTo(VT); - - // Otherwise, we have to insert explicit sign or zero extends. Note - // that we could insert sign extends for ALL conditions, but zero extend - // is cheaper on many machines (an AND instead of two shifts), so prefer - // it. - switch (cast<CondCodeSDNode>(CC)->get()) { - default: assert(0 && "Unknown integer comparison!"); - case ISD::SETEQ: - case ISD::SETNE: - case ISD::SETUGE: - case ISD::SETUGT: - case ISD::SETULE: - case ISD::SETULT: - // ALL of these operations will work if we...

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set

...etDebugLoc(); > + EVT VT = Op.getValueType(); > + > + SDValue LHS = Op.getOperand(0); > + SDValue RHS = Op.getOperand(1); > + SDValue True = Op.getOperand(2); > + SDValue False = Op.getOperand(3); > + SDValue CC = Op.getOperand(4); > + ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); > + SDValue Temp; > + > + // LHS and RHS are guaranteed to be the same value type > + EVT CompareVT = LHS.getValueType(); > + > + // We need all the operands of SELECT_CC to have the same value type, so if > + // necessary we need to convert LHS and RHS...