search for: computerelatedregclasses

Displaying 4 results from an estimated 4 matches for "computerelatedregclasses".

2007 May 09
0
[LLVMdev] EquivalenceClasses
...represent any binary relation (if you chose binary matrix representation I'd recommend using BitSetVector data structure found in include/llvm/ADT directory). FYI, in linear scan register allocator EquivalenceClasses object is used to divide register classes via "alias" relation. See ComputeRelatedRegClasses method in RegAllocLinearScan.cpp. Anton. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070510/e6b9af86/attachment.html>
2007 May 09
2
[LLVMdev] EquivalenceClasses
Can someone explain the terminology used in the Doxygen comments for EquivalenceClasses? Specifically, what is a "Leader" as opposed to other members of an equivalence class? Say, for example, I want to create a set of equivalence classes to specify subset relationships. Imagine B is a subset of A, C is a subset of B, E is a subset of D and D has no relation to any other set. I'd
2007 Jul 13
0
[LLVMdev] [PATCH] Re: Pluggable Register Coalescers
...gisterInfo(); li_ = &getAnalysis<LiveIntervals>(); + RegisterCoalescer &coalescer = getAnalysis<RegisterCoalescer>(); + + coalescer.invoke(fn, *this); + // If this is the first function compiled, compute the related reg classes. if (RelatedRegClasses.empty()) ComputeRelatedRegClasses(); Index: llvm/lib/CodeGen/RegAllocLocal.cpp =================================================================== --- llvm/lib/CodeGen/RegAllocLocal.cpp (revision 58818) +++ llvm/lib/CodeGen/RegAllocLocal.cpp (working copy) @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #in...
2007 Jul 11
3
[LLVMdev] Pluggable Register Coalescers
On Jul 11, 2007, at 11:39 AM, David Greene wrote: > On Wednesday 11 July 2007 12:41, Tanya M. Lattner wrote: > >> I think the coalescer should be flexible enough to be run >> independent of >> the register allocator. For example, you may want to expose the >> copies >> induced by transforming out of SSA to the scheduler. If the >> scheduler is