Displaying 9 results from an estimated 9 matches for "computeoperandlatency".
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...9; with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set this field with 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses the 'WriteResourceID' field of 'MCWriteLatencyEntry' in 'computeOperandLatency' function. I think the pair of latency and write resource for defintion will be useful to check conflicts of resources. As reference, I have attached simple patch.
Thanks,
JinGu Kang
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Index: utils/TableGen/SubtargetEmitter.cpp
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2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
...#39;Write' of defition is
>> referenced by a 'ReadAdvance'. If we always set this field with
>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>> 'computeOperandLatency' function. I think the pair of latency and
>> write resource for defintion will be useful to check conflicts of
>> resources. As reference, I have attached simple patch.
>>
>> Thanks,
>> JinGu Kang
>>
>
2013 Apr 30
1
[LLVMdev] Instruction Scheduling - migration from v3.1 to v3.2
...gt; v3.1 to v3.2 codebase. This has mostly gone well except that instruction
> latency scheduling is no longer happening.
>
> The people who implemented this previously sub-classed 'ScheduleDAGInstrs'
> and implemented the virtual methods 'computeLatency' and
> 'computeOperandLatency'. However, these methods have been removed from
> 'ScheduleDAG' and 'ScheduleDAGInstrs' so are no longer invoked on our
> implementation. Instead, the correct approach seems to implement a
> sub-class of 'TargetSchedModel'.
>
> When I had a look at how...
2013 Apr 26
0
[LLVMdev] Instruction Scheduling - migration from v3.1 to v3.2
...r for our processor from the
v3.1 to v3.2 codebase. This has mostly gone well except that instruction
latency scheduling is no longer happening.
The people who implemented this previously sub-classed 'ScheduleDAGInstrs'
and implemented the virtual methods 'computeLatency' and
'computeOperandLatency'. However, these methods have been removed from
'ScheduleDAG' and 'ScheduleDAGInstrs' so are no longer invoked on our
implementation. Instead, the correct approach seems to implement a
sub-class of 'TargetSchedModel'.
When I had a look at how other targets dealt with...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
...t;>>> referenced by a 'ReadAdvance'. If we always set this field with
>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>>>> 'computeOperandLatency' function. I think the pair of latency and
>>>> write resource for defintion will be useful to check conflicts of
>>>> resources. As reference, I have attached simple patch.
>>>>
>>>> Thanks,
>>>> JinGu Kang
>>>>
>
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST:
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...d by a 'ReadAdvance'. If we always set this field with
>>>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>>>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>>>>>> 'computeOperandLatency' function. I think the pair of latency and
>>>>>> write resource for defintion will be useful to check conflicts of
>>>>>> resources. As reference, I have attached simple patch.
>>>>>>
>>>>>> Thanks,
>>>>>&g...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...#39;. If we always set this field with
>>>>>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>>>>>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>>>>>>>> 'computeOperandLatency' function. I think the pair of latency and
>>>>>>>> write resource for defintion will be useful to check conflicts of
>>>>>>>> resources. As reference, I have attached simple patch.
>>>>>>>>
>>>>>>>>...
2017 Apr 03
2
Scheduler: modelling long register reservations?
Hello,
My out-of-tree target features some high latency instructions (let's call them FXLV). When an FXLV issues, it reserves its destination register and execution continues; if a subsequent instruction attempts to read or write that register, the pipline will stall until the FXLV completes. I have attempted to encode this constraint in the machine scheduler (excerpt at bottom of email).