Displaying 2 results from an estimated 2 matches for "computenumsignbitsfortargetnode".
2008 Dec 12
0
[LLVMdev] i1 promotion issue (again)
On Fri, Dec 12, 2008 at 11:42 AM, Scott Michel <scottm at aero.org> wrote:
> The alternative is to do fairly deep inspection of brconds to eliminate the
> truncate, which eventually gets expanded into:
> (i8:sext_in_reg (i8:truncate (i32:setcc ...)))
Have you tried implementing computeMaskedBitsForTargetNode for your
setcc nodes? If you have, I think DAGCombiner should take care
2008 Dec 12
4
[LLVMdev] i1 promotion issue (again)
Background: The Cell SPU does not have condition registers in the
normal sense. It fits the "zero or negative one" model, preferably
with an i32 register, which is what getSetCCResultType() will return.
Problem: LegalizeTypes promotes i1 to i8 via an i32 setcc, i.e., the
generated type legalization is:
(i8:truncate (i32:setcc i32:lhs, i32:rhs, ch:cond))
How do I keep