search for: computemaskedbitsfortargetnode

Displaying 7 results from an estimated 7 matches for "computemaskedbitsfortargetnode".

2008 Nov 21
2
[LLVMdev] computeMaskedBitsforTargetNode
Can someone explain what this function is supposed to do? I've looked at PowerPC, Sparc, etc.. and can't really figure out what I should be doing here. Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part
2008 Dec 12
0
[LLVMdev] i1 promotion issue (again)
On Fri, Dec 12, 2008 at 11:42 AM, Scott Michel <scottm at aero.org> wrote: > The alternative is to do fairly deep inspection of brconds to eliminate the > truncate, which eventually gets expanded into: > (i8:sext_in_reg (i8:truncate (i32:setcc ...))) Have you tried implementing computeMaskedBitsForTargetNode for your setcc nodes? If you have, I think DAGCombiner should take care of the necessary simplification. -Eli
2008 Dec 12
2
[LLVMdev] i1 promotion issue (again)
Hi Eli, > Have you tried implementing computeMaskedBitsForTargetNode for your > setcc nodes? If you have, I think DAGCombiner should take care of the > necessary simplification. he doesn't need to: the DAG combiner knows all about SetCC values, and should simplify this already. Ciao, Duncan.
2008 Dec 12
4
[LLVMdev] i1 promotion issue (again)
Background: The Cell SPU does not have condition registers in the normal sense. It fits the "zero or negative one" model, preferably with an i32 register, which is what getSetCCResultType() will return. Problem: LegalizeTypes promotes i1 to i8 via an i32 setcc, i.e., the generated type legalization is: (i8:truncate (i32:setcc i32:lhs, i32:rhs, ch:cond)) How do I keep
2008 Dec 12
0
[LLVMdev] i1 promotion issue (again)
On Fri, Dec 12, 2008 at 12:42 PM, Duncan Sands <baldrick at free.fr> wrote: > Hi Eli, > >> Have you tried implementing computeMaskedBitsForTargetNode for your >> setcc nodes? If you have, I think DAGCombiner should take care of the >> necessary simplification. > > he doesn't need to: the DAG combiner knows all about SetCC values, > and should simplify this already. Oh, this is ISD::SETCC? SelectionDAG::ComputeNumSignB...
2008 Dec 13
2
[LLVMdev] i1 promotion issue (again)
...is being custom lowered. Hence, DAGCombiner isn't doing me much good. -scooter On Dec 12, 2008, at 1:13 PM, Eli Friedman wrote: > On Fri, Dec 12, 2008 at 12:42 PM, Duncan Sands <baldrick at free.fr> > wrote: >> Hi Eli, >> >>> Have you tried implementing computeMaskedBitsForTargetNode for your >>> setcc nodes? If you have, I think DAGCombiner should take care >>> of the >>> necessary simplification. >> >> he doesn't need to: the DAG combiner knows all about SetCC values, >> and should simplify this already. > > Oh, this i...
2014 May 14
3
[LLVMdev] s/ComputeMaskedBits/ComputeKnownBits/g ?
On 13 May 2014 21:27, Rafael EspĂ­ndola <rafael.espindola at gmail.com> wrote: > On 13 May 2014 14:33, Jay Foad <jay.foad at gmail.com> wrote: >> I've always found the name ComputeMaskedBits a bit unintuitive, and >> since r154011 it's even worse because there is no masking going on >> whatsoever: >> >>