search for: computeinterv

...the BB dump. entry (0x8503c80, LLVM BB @0x8501af0, ID#0): Live Ins: %R0 %R1 %reg1024 = ORI %R0<kill>, 0 %reg1025 = ORI %R1<kill>, 0 V4R0 is getting killed because handleLiveInRegister() is called on all results of getAliasSet() for each of the liveins (this is in LiveIntervals::computeIntervals() ). handleRegisterDef() does a similar thing where calls handlePhysicalRegisterDef() on all members of getAliasSet() returned for the def, which also triggers this problem. Is it calling handle*() on the alias set of a register thats the culprit, or is it some mishandling in KillsRegist...

...0, LLVM BB @0x8501af0, ID#0): > Live Ins: %R0 %R1 > %reg1024 = ORI %R0<kill>, 0 > %reg1025 = ORI %R1<kill>, 0 > > V4R0 is getting killed because handleLiveInRegister() is called on > all results of getAliasSet() for each of the liveins (this is in > LiveIntervals::computeIntervals() ). > > handleRegisterDef() does a similar thing where calls > handlePhysicalRegisterDef() on all members of getAliasSet() returned > for the def, which also triggers this problem. > > Is it calling handle*() on the alias set of a register thats the > culprit, or is it some...

...ng similar to this in the past, though without the coalescing part. As I was interested in spilling, coalescing didn't matter to me. I approached this in a simple but possibly inelegant way, by integrating it into the LiveIntervals pass itself. In LiveIntervals::runOnMachineFunction, after the computeIntervals() call that does the actual work of the live interval analysis, I call my scheduler. After scheduling, I simply do the following: // Fix up kill information for live intervals. Rescheduling may often have // changed which instruction is a value's last use, and we must update // kill...

...LiveInterval&) + 3910 7 llc.hg 0x0000000000888429 llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::MachineInstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int) + 409 8 llc.hg 0x000000000088ade0 llvm::LiveIntervals::computeIntervals() + 2496 9 llc.hg 0x000000000088b56f llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&) + 447 10 llc.hg 0x00000000007b3493 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 115 11 llc.hg 0x0000000000a79ec0 llvm::FPPassManager::runOnFun...

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch?

On May 17, 2010, at 9:09 PM, Rafael Espindola wrote: >> The fast and local register allocators are meant to be used on unoptimized code, a 'Debug build'. While they do work on optimized code, they do not give good results. Their primary goal is compile time, not code quality. > > Yes, we have a somewhat uncommon use case. It is fine to spend time > optimizing bitcode (LTO

> The fast and local register allocators are meant to be used on unoptimized code, a 'Debug build'. While they do work on optimized code, they do not give good results. Their primary goal is compile time, not code quality. Yes, we have a somewhat uncommon use case. It is fine to spend time optimizing bitcode (LTO is a OK), but we want to make the final IL -> Executable translation

On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote: > While beginning to add vector registers to a back end I came across > the following problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0

While beginning to add vector registers to a back end I came across the following problem: as soon as I define two sets of registers that have a many-to-one mapping the live interval pass appears to double- kill the mapped-onto register. I have the following excerpts from my RegisterInfo.td. def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; def R0 : Rg<0 ,