search for: computedatalayout

Displaying 7 results from an estimated 7 matches for "computedatalayout".

2017 Aug 22
2
Subtarget Initialization in <ARCH>TargetMachine constructor
...const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), OL), TLOF(make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } LanaiTargetMachine::LanaiTargetMachine(const...
2014 Jan 06
2
[LLVMdev] Why do X86_32TargetMachine and X86_64TargetMachine classes exist?
...Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), + : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, Triple(TT).getArch()) DL(computeDataLayout(*getSubtargetImpl())), InstrInfo(*this), -- David Woodhouse Open Source Technology Centre David.Woodhouse at intel.com Intel Corporation -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...[repo]/llvm/include/llvm/IR/Intrinsics.td [repo]/llvm/include/llvm/CodeGen/MachineValueType.h [repo]/llvm/lib/IR/ValueTypes.cpp [repo]/llvm/include/llvm/CodeGen/ValueTypes.td The reason I need this type, v128i64, is that pointers have size 64 bits - my ConnexTargetMachine::computeDataLayout() returns normally string "e-m:e-p:64:32-i32:32:32-i64:64-n32:32-S128", since my back end basically extends with vector instructions the LLVM BPF back end. So, at instruction selection it lowers the <128 x i16> value to <128 x i64>, since pointers have 64 bits, which w...
2017 Aug 23
2
Subtarget Initialization in <ARCH>TargetMachine constructor
...Optional<Reloc::Model> RM, >> Optional<CodeModel::Model> CM, >> CodeGenOpt::Level OL, bool >> isLittle) >> : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), >> TT, >> CPU, FS, Options, getEffectiveRelocModel(TT, RM), >> getEffectiveCodeModel(CM), OL), >> TargetABI(computeTargetABI(TT, CPU, Options)), >> TLOF(createTLOF(getTargetTriple(...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -
2015 Jan 27
7
[LLVMdev] Embedding cpu and feature strings into IR and enabling switching subtarget on a per function basis
I've been investigating what is needed to ensure command line options are passed to the backend codegen passes during LTO and enable compiling different functions in a module with different command line options (see the links below for previous discussions). http://thread.gmane.org/gmane.comp.compilers.llvm.devel/78855 http://thread.gmane.org/gmane.comp.compilers.llvm.devel/80456 The command
2013 Dec 31
4
[LLVMdev] [Patch][RFC] Change R600 data layout
Hi, I've prepared patches for both LLVM and Clang to change the datalayout for R600. This may seem like a bold move, but I think it is warranted. R600/SI is a strange architecture in that it uses 64bit pointers but does not support 64 bit arithmetic except for load/store operations that roughly map onto getelementptr. The current datalayout for r600 includes n32:64, which is odd