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...ion Based on SSA-Graphs SCOPES 2003 http://springerlink.metapress.com/content/83cj0ebgtm998hj8 -- --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien F: (+431) 58801-18598 Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

...ntation on how to > do it? Dunno. Last time I looked, the documentation of clang's command line flags disagreed with reality, and the -ccc-host-triple flag wasn't documented anywhere. This might have changed in the meantime. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...ES 2003 > http://springerlink.metapress.com/content/83cj0ebgtm998hj8 > > -- > --------------------------------------------------------------------- > Dietmar Ebner > CD Laboratory - Compilation Techniques for Embedded Processors > Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at > Technische Universitaet Wien F: (+431) 58801-18598 > Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 > 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner > > _______________________________________________ > LLVM Developers mailing list &...

...es LLVM place casts into > different virtual registers, or do I need to include casting of floats to > integers or vice versa when I see ADD i32 float i32? The instruction selector creates all necessary conversion instructions. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...++time; } else { assert( 0 && "The register is always defining or used." ); } } } } } } Thanks, Jeff Kunkel On Sun, Aug 29, 2010 at 8:45 AM, Gergö Barany <gergo at complang.tuwien.ac.at>wrote: > On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > > What I need to know is how to access the machine register classes. Also, > I > > need to know which virtual register is to be mapped into each specific > > register class. I assume there...

...of optimal code generation techniques for explicit parallel processors at the Vienna University of Technology. We seek people familiar with LLVM and/or with some background of integer linear programming and VLIW code generation. If interested, please respond directly to Andreas Krall: andi at complang.tuwien.ac.at http://www.complang.tuwien.ac.at/andi Thanks, Dietmar -- Dietmar Ebner Computer Languages Group E: ebner at complang.tuwien.ac.at Vienna University of Technology T: (+431) 58801-58521 Argentinierstrasse 8 / E1851 F: (+431) 58801-18598 1040 Wien, Austria...

...which I am currently struggling with. It's all in a very messy pre-prototype stage, but I'm getting there and will be happy to contribute my work when it's nice and clean. Thanks for the feedback, Jakob and Evan. Gergo -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

...re-prototype stage, but I'm getting there and will be > happy to contribute my work when it's nice and clean. Sounds great. Thanks. Evan > > Thanks for the feedback, Jakob and Evan. > > > Gergo > -- > Gergö Barany, research assistant gergo at complang.tuwien.ac.at > Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,

...inclusion, i would be willing to bring the code in shape and make changes where necessary. - dietmar -- --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien F: (+431) 58801-18598 Argentinierstrasse 8 / E1851 T: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

Excellent, I've implemented my own PBQP register allocator and solved the issue very painlessly. Now onto those more interesting problems! Thanks for your suggestion, Fraser On Fri, Oct 5, 2012 at 9:26 AM, Gergö Barany <gergo at complang.tuwien.ac.at>wrote: > On Thu, Oct 04, 2012 at 16:20:53 +0100, Fraser Cormack wrote: > > This architecture has two single-ported register files. Each instruction > > can only read one operand from each register file, but can write to > either. > > Even if you can't ex...

Hello list, I wonder if llvm/Clang can compile C or C++ for ARM from on x86. http://comments.gmane.org/gmane.comp.compilers.clang.devel/8896 The talk above answered 'NO' to my question, which means Clang is not yet able to cross compile for ARM on X86. Is the answer still correct for my question? I saw somewhere that Clang supports ARM on Darwin only. Then is the cross compiling

...patch (which I have updated to llvm 2.4 at some point). - Dietmar [1] http://www.kegel.com/crosstool/ --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien T: (+431) 58801-58521 Argentinierstrasse 8 / E1851 F: (+431) 58801-18598 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

...estcase, but i did not run the testsuites. florian -- Brandner Florian CD Laboratory - Compilation Techniques for Embedded Processors Institut für Computersprachen E185/1 Technische Universität Wien Argentinierstraße 8 / 185 A-1040 Wien, Austria Tel.: (+431) 58801-58521 E-Mail: brandner at complang.tuwien.ac.at -------------- next part -------------- A non-text attachment was scrubbed... Name: tailup-loop.c Type: text/x-csrc Size: 149 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080611/43841b2a/attachment.c> -------------- next part ----------...

...onversion in an Itanium Link-Time Optimizer http://systems.cs.colorado.edu/EPIC2/papers/s3-3-snavely.pdf --------------------------------------------------------------------- Dietmar Ebner CD Laboratory - Compilation Techniques for Embedded Processors Institut fuer Computersprachen E: ebner at complang.tuwien.ac.at Technische Universitaet Wien T: (+431) 58801-18598 Argentinierstrasse 8 / E1851 F: (+431) 58801-58521 1040 Wien, Austria W: www.complang.tuwien.ac.at/cd/ebner

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hello, is it possible to compile just an subproject? For example, just llc or lli? Cheers. Beckert. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120503/c20aa7b1/attachment.html>

Hello Everyone, Would you please send me any links to documentation on LLVM stack? I am particularly interested in knowing how each instruction in an LLVM bit code file(.ll file) affects its stack. To be specific, is it possible to map an LLVM program as operations on a stack? Thanks, Amruth

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent: