search for: compilerwriterinfo

The ISA & encoding is documented in the comments and diagrams of lib/Target/Lanai/LanaiInstrFormats.td. If that makes sense I'll add a link to this tablegen in docs/CompilerWriterInfo.rst. Thanks, Jacques On Tue, Feb 9, 2016 at 2:12 PM, Sean Silva <chisophugis at gmail.com> wrote: > Do you have a psABI document? Or an ISA reference? Or an encoding > reference? > > I know at least the encoding reference is missing for AArch64, so it's not > a huge dea...

I found this the other day while surfing the web. For those wanting to understand about Mips 16, it's a very easy and quick read. If you already understand Mips, it will make the llvm Mips16 port much easier to understand. It has just the overview information one needs. Of course full Mips 16 documentation is available at Mips.com. -------------- next part -------------- A non-text

Please add this to <http://llvm.org/docs/CompilerWriterInfo.html> (docs/CompilerWriterInfo.rst) -- Sean Silva

On 01/21/2013 03:28 PM, Sean Silva wrote: > Please add this to <http://llvm.org/docs/CompilerWriterInfo.html> > (docs/CompilerWriterInfo.rst) > > -- Sean Silva I will. I owe a very long mips16 write up , especially for floating point when I'm done. It's very complicated the way they implemented hard float in gcc and it is not documented. It took me some thinking and study to unr...

On 7/25/2016 1:46 PM, Chandler Carruth via llvm-dev wrote: > And perhaps there is a spec for AMDGPU or Hexagon, but even when I've > asked developers on those backends about problems, they've not pointed > be at the published ISA documentation. The Hexagon ISA is now available at https://developer.qualcomm.com/software/hexagon-dsp-sdk/tools It's the "Programmer's

...ruction sets differ in how instructions are encoded. Basically, we can develop C-SKY V2 as prefer, and the ISA doc and ABI doc can be referred at following links. (The links are not stable, and the address may be changed). The links will be added and updated constantly later at http://llvm.org/docs/CompilerWriterInfo.html. ISA: https://github.com/c-sky/csky-doc/blob/master/CSKY%20Architecture%20user_guide.pdf ABI: https://github.com/c-sky/csky-doc/blob/master/C-SKY_V2_CPU_Applications_Binary_Interface_Standards_Manual.pdf Here is the first patch to introduce the CSKY target, https://reviews.llvm.org/D86269. Fe...

Hi all, We would like to contribute a new backend for the Lanai processor (derived from the processor described in [1]). Lanai is a simple in-order 32-bit processor with: * 32 32-bit registers, including: * 2 registers with fixed values; * 4 used for program state tracking (PC, SP, FP, RCA); * 2 reserved for explicit usage by user (R10 and R11), used in threading library; * Up

On 26 July 2016 at 00:08, Chris Lattner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > It is unquestionably easier for a contributor to land their backend in-tree > than to maintain it out-of-tree. This is because landing it in tree shifts > the maintenance burden from the *contributor* to the *community*. If there > is low value to the community, then this is a "bad

On Mon, Aug 21, 2006 at 05:09:10PM -0300, Rafael Espíndola wrote: > I am trying to add support for select_cc. In ARM it can be implemented > with: [snip] Speaking of new backends, there is a document that lists some architecture docs: http://llvm.org/docs/CompilerWriterInfo.html . There is a link to the GCC library as well, which is rather extensive and may be helpful in writing a new backend. If you find any good references to optimization manuals, etc. that aren't mentioned there, please send them along. -- Misha Brukman :: http://misha.brukman.net

...ype from text assembly 4.llvm/lib/AsmReader/llvmAsmParser.y: add a token for that type also, this file need to add a meta data that set charset to utf-8 such as <meta http-equiv="content-type" content="text/html; charset=UTF-8"> and also many other files:. .\llvm\docs\CompilerWriterInfo.html 1.Hardware Other x86-specific information need change the url of •Calling conventions for different C++ compilers and operating systems the new one is 3.Miscellaneous resources http://www.agner.org/optimize/#manuals I think need to add The DWARF Debugging Standard http://www.dwarfstd.org/...

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction has no results. It only alters the CPSR (current program

Hi all, I’m pretty new to the list, and to LLVM in general, so please excuse my extreme newbiesness. I’m trying to figure out what would be the appropriate way to implement move semantics. I’ve been trying to dump the IR produced by clang with some basic C++ snippet, but I’m afraid it didn’t help me much. Here’s the example I’ve been playing with (in C++): struct S { S() noexcept: x(new int)

...that the C++ ABI is phrased in terms of the underlying C ABI (which is processor-specific (and generally not OS-specific unless you care about Windows vs non-Windows)), so familiarity with the C ABI is useful too; documents for the C ABI of different processors can be found in http://llvm.org/docs/CompilerWriterInfo.html e.g. the "X86 and X86-64 SysV psABI". The C ABI may seem overwhelming (lots of processor details, corner cases, etc.), but the basic gist is that there's a list of registers and each argument is assigned in turn from that list (if the register list is exhausted, the rest are pass...