Displaying 6 results from an estimated 6 matches for "combinetopreindexedloadstor".
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combinetopreindexedloadstore
2013 Apr 08
1
[LLVMdev] Is r174746 broken on ARM?
...th for ARM and Thumb2, in getARMIndexedAddressParts
and getT2IndexedAddressParts, respectively, in a calls to:
Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
^^^^^
here!
So you don't need to invert it one more time in DAGCombiner::CombineToPreIndexedLoadStore.
Dmitry
2013 Apr 04
0
[LLVMdev] Is r174746 broken on ARM?
...0 also fixes the problem. I'm trying to fix it myself, but
> still have no good ideas; so it would be great to have an advice
> from you.
r174746 is specifically related to pre-increment loads and stores. I think that the first step is to narrow down the problematic case. In DAGCombiner::CombineToPreIndexedLoadStore, there is a loop which starts with:
SmallVector<SDNode *, 16> OtherUses;
if (isa<ConstantSDNode>(Offset))
for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(),
E = BasePtr.getNode()->use_end(); I != E; ++I) {
SDNode *Use = *I;
1. Make the loop ski...
2013 Apr 04
2
[LLVMdev] Is r174746 broken on ARM?
Hello Hal,
I have a strong suspicion that your constant folding optimization
introduced at r174746 is broken on ARM. There is a bug about it:
http://llvm.org/bugs/show_bug.cgi?id=15581
There is no such issue with 3.2, and reverting r174746 on top of
r178740 also fixes the problem. I'm trying to fix it myself, but
still have no good ideas; so it would be great to have an advice
from you.
2010 Oct 08
1
[LLVMdev] llvm-gcc: code generated for pre- and post-increment
...*p;
void func(void)
{
c = *++p;
}
then I get (with llvm-gcc 4.2.1):
%0 = load i8** @p, align 4
%1 = getelementptr inbounds i8* %0, i32 1
store i8* %1, i8** @p, align 4
%2 = load i8*, %1, align 1
store i* %2m i8* @c, align 1
I think the position of the first store is preventing
DAGCombiner::CombineToPreIndexedLoadStore from folding the base
pointer (test #3 out of the 4 tests it makes). If I move that store
into p to the end of the code then it's happy to fold it.
Why does llvm-gcc emit llvm code that seems to preclude the combiner
from ever being able to combine a pre-increment/decrement? Given that...
2011 Jun 24
2
[LLVMdev] Infinite loop in llc on ARMv7 (LLVM HEAD from June 17)
...>::pop_back_val
(this=0x7ee90b38)
at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:340
#3 0x00a6f074 in llvm::SDNode::isPredecessorOf (this=0x641bb08,
N=0x6212a40)
at
/export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5703
#4 0x00a057c8 in CombineToPreIndexedLoadStore (this=0x7ee90f84,
N=0x6238040)
at
/export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5707
#5 0x00a07544 in visitLOAD (this=0x7ee90f84, N=0x6238040)
at
/export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6011
#6 0x009e307c in visit (this=0...
2011 Jun 24
0
[LLVMdev] Infinite loop in llc on ARMv7 (LLVM HEAD from June 17)
...0x7ee90b38)
> at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:340
> #3 0x00a6f074 in llvm::SDNode::isPredecessorOf (this=0x641bb08,
> N=0x6212a40)
> at
> /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5703
> #4 0x00a057c8 in CombineToPreIndexedLoadStore (this=0x7ee90f84,
> N=0x6238040)
> at
> /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5707
> #5 0x00a07544 in visitLOAD (this=0x7ee90f84, N=0x6238040)
> at
> /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6011
> #...