search for: combineto

2015-07-08 17:58 GMT+02:00 escha <escha at apple.com>: > [...] > > If you want to “revert" this sort of thing, you can do it at Select() time > or PreprocessISelDAG(), which is what I did on an out-of-tree backend to > turn add X, -C into sub X, C on selection time. This still lets all the > intermediate optimizations take advantage of the canonicalization. > >

...o, LHSOne; TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, LHSZero, LHSOne, Depth+1); // If the LHS already has zeros where RHSC does, this and is dead. if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) return TLO.CombineTo(Op, Op.getOperand(0)); As neither of these are virtual functions, we cannot create an workaround hack for our backend to easily circumvent this bug. It would now seem that TCE users cannot use the default LLVM 2.8 but we'll have to distribute our own patch to disable the invalid drop...

...This could be a handy way to create new targeted test cases at the IR/MIR level. Something like this would have helped triage issues like llvm.org/ <http://llvm.org/>PR25630 as well. > > 2) Assert that combines preserve debug info. > > If there's an important API like "CombineTo(From, To)", it could be useful to assert that the To node has at least as much debug info as the From node. I'm experimenting with this in SelectionDAG (llvm.org/PR35338 <http://llvm.org/PR35338>). I don't yet know where these asserts belong, how strict they should be, or if they...

...TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, > LHSZero, LHSOne, Depth+1); > // If the LHS already has zeros where RHSC does, this and is dead. > if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) > return TLO.CombineTo(Op, Op.getOperand(0)); > > > > > > As neither of these are virtual functions, we cannot create an > workaround hack for our backend to easily circumvent this bug. > > > > > It would now seem that TCE users cannot use the default LLVM 2.8 but > we...

> On Nov 13, 2017, at 11:53 AM, Vedant Kumar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Amara, > >> On Nov 10, 2017, at 9:12 AM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi everyone, >> >> This RFC concerns the design and architecture of a generic machine

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set