search for: combineincdecvector

...nge DAGCombiner so that it process the nodes in topological order. Doing so is not difficult per se, but this creates various improvements and regression to the existing test suite. I'd like to work through as many of the regressions as possible ahead of time. One source of such regressions is combineIncDecVector in the X86 backend. It changes (add X, 1) into (sub X, -1) in order to be able to use the pcmpeq instruction. This is all well and good, but numerous paterns are matching an add rather than a sub, and in fact, DAGCombiner does the inverse transform by itself as it consider the add form to be canon...

...as well From: Amaury Séchet <deadalnix at gmail.com> Sent: Monday, August 26, 2019 10:48 AM To: Topper, Craig <craig.topper at intel.com>; llvm-dev at redking.me.uk; efriedma at quicinc.com; lebedev.ri at gmail.com; llvm-dev <llvm-dev at lists.llvm.org> Subject: LLVM X86 backend combineIncDecVector's transform Hi all, As you knwo already, I'm trying to change DAGCombiner so that it process the nodes in topological order. Doing so is not difficult per se, but this creates various improvements and regression to the existing test suite. I'd like to work through as many of the regres...

...ential conflicts when I added that code. Delayed combine, custom lowering, or DAGToDAGISel all seem like viable options to me. On Mon, Aug 26, 2019 at 2:04 PM Roman Lebedev <lebedev.ri at gmail.com> wrote: > I have previously posted these two patches: > > [X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to > X86DAGToDAGISel > https://reviews.llvm.org/D62327 > > [DAGCombine][X86][AArch64][AMDGPU][MIPS][PPC] (sub x, c) -> (add x, > -c) vector edition. > https://reviews.llvm.org/D62341 > > While they got stuck since i wasn't really interested in them...