search for: combine2

...till the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i have made necessary changes in X86ISelLowering.cpp. and rebuild llvm. then when i use the command -view-dag-combine2-dags i get the required output in graph but the following error on console: LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 t7: v64i32 = add t6, t4 t6: v64i32,ch = load<LD256[bi...

We've got both an sqrtf and an expf opcode in our architecture. If I call sqrt() on the C side, I see the sqrtf opcode show up in the generated assembly. However, if I call exp() on the C side, I don't see the expf opcode show up on the generated assembly, I see a call to an exp function from libm. Here's what we've got in our TargetInstrinfo.td file for both of these

...which will expose optimization opportunities. Or is there a place > that is appropriate to insert theses ? > > At least in theory, SelectionDAG is supposed to be able to do a lot of > these kind of optimizations. The goal is to do legalization, then clean up > the results of that in combine2. > > —escha > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists...

...f there are 128 >>>> elements in loop then it should break it into 2 v64i32 instructions. >>>> >>>> in order to do this i have made necessary changes in >>>> X86ISelLowering.cpp. and rebuild llvm. then when i use the >>>> command -view-dag-combine2-dags i get the required output in graph but >>>> the following error on console: >>>> >>>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* >>>> @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef...

Hi all, Some non trivial legalization of operations which aren't supported by the backend would benefit from having the optimizer pass on them. I noticed some example trying to optimize various pieces of code over the past weeks. One offender is the cttz/ctlz intrinsic when defined on 0. On X86, BSR and NSF are undefined on 0, and only recent CPU have the LZCNT and TZCNT instructions that

...s, it thinks the Expand legalize action means to unroll the vector. This isn't necessary and not what I wanted. Is there a way to get one and not the other? I don't want the unroll aspect of the Expand action. I changed to a Custom lowering and duplicated the FADD+FNEG action, but the dag-combine2 stage moved this back to FSUB, which then failed to pattern match in Select. That code checks for !LegalOperations || TLI.isLegalorCustom(FSUB), which of course is true for this case. Suggestions? Thanks, Joe -------------- next part -------------- An HTML attachment was scrubbed... URL: <http...

...n greedy; in practice most optimization goals seem to be representable through heuristics on the regular selection algorithm, at least for real machines. Additionally, I kind of suspect that there is far more to gain from better transformations during instruction lowering (e.g. in Combine1/Legalize/Combine2) than from better ordering in Select(). —escha > On Mar 28, 2018, at 3:31 AM, Ivan Kulagin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Is the algorithm described in the article "Near-Optimal Instruction > Selection on DAGs > (https://llvm.org/pubs/2008-CGO-DagI...

Is the algorithm described in the article "Near-Optimal Instruction Selection on DAGs (https://llvm.org/pubs/2008-CGO-DagISel.html)" really used in llvm instruction selection? I've studied implementation (SelectionDAGISel.cpp) and I see that instructions are selected by target specific MatcherTable generated by llvm-tblgen. In the implementation the first matching pattern from

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

...i want it to retain v64i32. like if > there are 128 elements in loop then it should break it into 2 > v64i32 instructions. > > in order to do this i have made necessary changes in > X86ISelLowering.cpp. and rebuild llvm. then when i use the > command -view-dag-combine2-dags i get the required output in graph > but the following error on console: > > LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x > i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, > t12, undef:i64 > t7: v64i32...

...into 4 v16i32. i want it to retain v64i32. like if there are 128 >> elements in loop then it should break it into 2 v64i32 instructions. >> >> in order to do this i have made necessary changes in X86ISelLowering.cpp. >> and rebuild llvm. then when i use the command -view-dag-combine2-dags i >> get the required output in graph but the following error on console: >> >> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a >> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >> t7: v64i32 = add...

...elements in loop then it should break it into 2 v64i32 instructions. >>>>>> >>>>>> in order to do this i have made necessary changes in >>>>>> X86ISelLowering.cpp. and rebuild llvm. then when i use the >>>>>> command -view-dag-combine2-dags i get the required output in graph >>>>>> but the following error on console: >>>>>> >>>>>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* >>>>>> @a to <64 x i32>*)](align=16)(tbaa=<0x30c...

...ions. >>>>>>>>>> >>>>>>>>>> in order to do this i have made necessary changes in >>>>>>>>>> X86ISelLowering.cpp. and rebuild llvm. then when i use the >>>>>>>>>> command -view-dag-combine2-dags i get the required output in >>>>>>>>>> graph but the following error on console: >>>>>>>>>> >>>>>>>>>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x >>>>>>>>&...

...gt;> in order to do this i have made necessary changes in >>>>>>>>>>>>>>>>>>>> X86ISelLowering.cpp. and rebuild llvm. then when i use the >>>>>>>>>>>>>>>>>>>> command -view-dag-combine2-dags i get the required >>>>>>>>>>>>>>>>>>>> output in graph but the following error on console: >>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>&...

...-02-22 18:07:45.236910] I [MSGID: 115013] [server-helpers.c:293:do_fd_cleanup] 0-scratch-server: fd cleanup on /download/work/kstovall/57910/combine1.log [2018-02-22 18:07:45.236966] I [MSGID: 115013] [server-helpers.c:293:do_fd_cleanup] 0-scratch-server: fd cleanup on /download/work/kstovall/57910/combine2.log [2018-02-22 18:07:45.237007] I [MSGID: 101055] [client_t.c:415:gf_client_unref] 0-scratch-server: Shutting down connection wheeler061-17519-2018/02/22-18:04:06:449987-scratch-client-1-2-0 [2018-02-22 18:07:45.262237] I [MSGID: 115029] [server-handshake.c:692:server_setvolume] 0-scratch-server:...