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By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property;...

By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their guest DTs but neglect to add the often-overlooked "dma-coherent" property;...

...60,10 +161,14 @@ static bool vring_use_dma_api(struct virtio_device *vdev) > > return true; > > > > /* > > - * On ARM-based machines, the DMA ops will do the right thing, > > - * so always use them with legacy devices. > > + * On ARM-based machines, the coherent DMA ops will do the right > > + * thing, so always use them with legacy devices. However, using > > + * non-coherent DMA when the host *is* actually coherent, but has > > + * forgotten to tell us, is going to break badly; since this situation > > + * already exists in th...

...60,10 +161,14 @@ static bool vring_use_dma_api(struct virtio_device *vdev) > > return true; > > > > /* > > - * On ARM-based machines, the DMA ops will do the right thing, > > - * so always use them with legacy devices. > > + * On ARM-based machines, the coherent DMA ops will do the right > > + * thing, so always use them with legacy devices. However, using > > + * non-coherent DMA when the host *is* actually coherent, but has > > + * forgotten to tell us, is going to break badly; since this situation > > + * already exists in th...

On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: > By forcing on DMA API usage for ARM systems, we have inadvertently > kicked open a hornets' nest in terms of cache-coherency. Namely that > unless the virtio device is explicitly described as capable of coherent > DMA by firmware, the DMA APIs on ARM and other DT-based platforms will > assume it is non-coherent. This turns out to cause a big problem for the > likes of QEMU and kvmtool, which generate virtio-mmio devices in their > guest DTs but neglect to add the often-overlooked "dma-cohe...

...ring_use_dma_api(struct virtio_device *vdev) > > > return true; > > > > > > /* > > > - * On ARM-based machines, the DMA ops will do the right thing, > > > - * so always use them with legacy devices. > > > + * On ARM-based machines, the coherent DMA ops will do the right > > > + * thing, so always use them with legacy devices. However, using > > > + * non-coherent DMA when the host *is* actually coherent, but has > > > + * forgotten to tell us, is going to break badly; since this situation > > > + *...

Hi All, I have two time series, each has length 354. I tried to calculate the coherency^2 between them, but the value I got is always 1. On a website, it says: " Note that if the ensemble averaging were to be omitted, the coherency (squared) would be 1, independent of the data". Does any of you know how to specify properly in R in order to get more useful coherency? The examples in

...ma_api(struct virtio_device *vdev) >>>> return true; >>>> >>>> /* >>>> - * On ARM-based machines, the DMA ops will do the right thing, >>>> - * so always use them with legacy devices. >>>> + * On ARM-based machines, the coherent DMA ops will do the right >>>> + * thing, so always use them with legacy devices. However, using >>>> + * non-coherent DMA when the host *is* actually coherent, but has >>>> + * forgotten to tell us, is going to break badly; since this situation >>>&g...

...ma_api(struct virtio_device *vdev) >>>> return true; >>>> >>>> /* >>>> - * On ARM-based machines, the DMA ops will do the right thing, >>>> - * so always use them with legacy devices. >>>> + * On ARM-based machines, the coherent DMA ops will do the right >>>> + * thing, so always use them with legacy devices. However, using >>>> + * non-coherent DMA when the host *is* actually coherent, but has >>>> + * forgotten to tell us, is going to break badly; since this situation >>>&g...

On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: > By forcing on DMA API usage for ARM systems, we have inadvertently > kicked open a hornets' nest in terms of cache-coherency. Namely that > unless the virtio device is explicitly described as capable of coherent > DMA by firmware, the DMA APIs on ARM and other DT-based platforms will > assume it is non-coherent. This turns out to cause a big problem for the > likes of QEMU and kvmtool, which generate virtio-mmio devices in their > guest DTs but neglect to add the often-overlooked "dma-cohe...

...doesn't make any sense. dma_*mb() explicitly does _NOT_ > > > cover the smp_*mb() part. > > > > > > Again, look at the ARM definitions, the smp_*mb() primitives use the > > > inner coherence stuff, while the dma_*mb() primitives use the outer > > > coherent stuff. > > > > Does outer coherent imply inner coherent? > > > > > the *mb() primitives cover both. > > I do not think so, but lets add Will, he dreams this stuff. Right, and I don't sleep well these days. Anyway, the outer-shareable domain (osh) is a super...

...doesn't make any sense. dma_*mb() explicitly does _NOT_ > > > cover the smp_*mb() part. > > > > > > Again, look at the ARM definitions, the smp_*mb() primitives use the > > > inner coherence stuff, while the dma_*mb() primitives use the outer > > > coherent stuff. > > > > Does outer coherent imply inner coherent? > > > > > the *mb() primitives cover both. > > I do not think so, but lets add Will, he dreams this stuff. Right, and I don't sleep well these days. Anyway, the outer-shareable domain (osh) is a super...

Currently, default behavior of O_DIRECT writes was allowing concurrent writing among nodes, no cluster coherency guaranteed (no EX locks was taken), it hurts buffered reads on other nodes by reading stale data from cache. The new mount option introduce a chance to choose two different behaviors for O_DIRECT writes: * coherency=full, as the default value, will disallow concurrent

...barriers to use dma_wmb/rmb > > That commit doesn't make any sense. dma_*mb() explicitly does _NOT_ > cover the smp_*mb() part. > > Again, look at the ARM definitions, the smp_*mb() primitives use the > inner coherence stuff, while the dma_*mb() primitives use the outer > coherent stuff. Does outer coherent imply inner coherent? > the *mb() primitives cover both.

...barriers to use dma_wmb/rmb > > That commit doesn't make any sense. dma_*mb() explicitly does _NOT_ > cover the smp_*mb() part. > > Again, look at the ARM definitions, the smp_*mb() primitives use the > inner coherence stuff, while the dma_*mb() primitives use the outer > coherent stuff. Does outer coherent imply inner coherent? > the *mb() primitives cover both.

Greetings, I would like to estimate a spectral coherence between two timeseries. The stats : spectrum() returns a coh matrix which estimates coherence (squared). A basic test which from which i expect near-zero coherence: x = rnorm(500) y = rnorm(500) xts = ts(x, frequency = 10) yts = ts(y, frequency = 10) gxy = spectrum( cbind( xts, yts ) ) plot( gxy $ freq, gxy $

...mmio the changes are very small: several new registers, > > > > that's all. You want this for proper 64 bit dma mask anyway. > > > > > > As I've said, virtio 1 will have exactly the same issue unless we start > > > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > > > devices correctly. > > > > > > > OK I read up on _CCA in ACPI spec. It says: > > The _CCA object returns whether or not a bus-master device supports > > hardware managed cache coherency. Expected values are 0 to indicate it >...

...mmio the changes are very small: several new registers, > > > > that's all. You want this for proper 64 bit dma mask anyway. > > > > > > As I've said, virtio 1 will have exactly the same issue unless we start > > > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > > > devices correctly. > > > > > > > OK I read up on _CCA in ACPI spec. It says: > > The _CCA object returns whether or not a bus-master device supports > > hardware managed cache coherency. Expected values are 0 to indicate it >...

...o just implement virtio 1. > > For mmio the changes are very small: several new registers, > > that's all. You want this for proper 64 bit dma mask anyway. > > As I've said, virtio 1 will have exactly the same issue unless we start > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > devices correctly. > > Will OK I read up on _CCA in ACPI spec. It says: The _CCA object returns whether or not a bus-master device supports hardware managed cache coherency. Expected values are 0 to indicate it is not supported, and 1 to indicate that it is support...

...o just implement virtio 1. > > For mmio the changes are very small: several new registers, > > that's all. You want this for proper 64 bit dma mask anyway. > > As I've said, virtio 1 will have exactly the same issue unless we start > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > devices correctly. > > Will OK I read up on _CCA in ACPI spec. It says: The _CCA object returns whether or not a bus-master device supports hardware managed cache coherency. Expected values are 0 to indicate it is not supported, and 1 to indicate that it is support...