search for: coherency

By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their...

By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate virtio-mmio devices in their...

...atch needed for ACPI). See below. Do you prefer this approach? Will --->8 >From f6ad4e331c26e7ba53132c8cc74e26f782391570 Mon Sep 17 00:00:00 2001 From: Will Deacon <will.deacon at arm.com> Date: Mon, 30 Jan 2017 17:28:31 +0000 Subject: [PATCH] of/address: Allow devices to report DMA coherency based on compatible string Some devices (e.g. virtio-mmio) are implicitly cache coherent with respect to DMA operations and therefore do not mandate the use of "dma-coherent" in their devicetree bindings. In order to ensure that these devices work correctly when using the DMA API, we ne...

...atch needed for ACPI). See below. Do you prefer this approach? Will --->8 >From f6ad4e331c26e7ba53132c8cc74e26f782391570 Mon Sep 17 00:00:00 2001 From: Will Deacon <will.deacon at arm.com> Date: Mon, 30 Jan 2017 17:28:31 +0000 Subject: [PATCH] of/address: Allow devices to report DMA coherency based on compatible string Some devices (e.g. virtio-mmio) are implicitly cache coherent with respect to DMA operations and therefore do not mandate the use of "dma-coherent" in their devicetree bindings. In order to ensure that these devices work correctly when using the DMA API, we ne...

On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: > By forcing on DMA API usage for ARM systems, we have inadvertently > kicked open a hornets' nest in terms of cache-coherency. Namely that > unless the virtio device is explicitly described as capable of coherent > DMA by firmware, the DMA APIs on ARM and other DT-based platforms will > assume it is non-coherent. This turns out to cause a big problem for the > likes of QEMU and kvmtool, which generate virtio-m...

...from @arm.com and not worry about breaking actual hardware. > >From f6ad4e331c26e7ba53132c8cc74e26f782391570 Mon Sep 17 00:00:00 2001 > From: Will Deacon <will.deacon at arm.com> > Date: Mon, 30 Jan 2017 17:28:31 +0000 > Subject: [PATCH] of/address: Allow devices to report DMA coherency based on > compatible string > > Some devices (e.g. virtio-mmio) are implicitly cache coherent with respect > to DMA operations and therefore do not mandate the use of "dma-coherent" > in their devicetree bindings. In order to ensure that these devices work > correctly...

Hi All, I have two time series, each has length 354. I tried to calculate the coherency^2 between them, but the value I got is always 1. On a website, it says: " Note that if the ensemble averaging were to be omitted, the coherency (squared) would be 1, independent of the data". Does any of you know how to specify properly in R in order to get more useful coherency? The...

...t; And then I can apply whatever comes from @arm.com and not > worry about breaking actual hardware. I'm actually seeing the exact same breakage in QEMU right now, so it's not fast model related at all. In QEMU we also don't properly set the dma-coherent flag, so we run into cache coherency problems. Alex

...t; And then I can apply whatever comes from @arm.com and not > worry about breaking actual hardware. I'm actually seeing the exact same breakage in QEMU right now, so it's not fast model related at all. In QEMU we also don't properly set the dma-coherent flag, so we run into cache coherency problems. Alex

On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: > By forcing on DMA API usage for ARM systems, we have inadvertently > kicked open a hornets' nest in terms of cache-coherency. Namely that > unless the virtio device is explicitly described as capable of coherent > DMA by firmware, the DMA APIs on ARM and other DT-based platforms will > assume it is non-coherent. This turns out to cause a big problem for the > likes of QEMU and kvmtool, which generate virtio-m...

On Thu, Dec 17, 2015 at 04:09:17PM +0100, Peter Zijlstra wrote: > On Thu, Dec 17, 2015 at 04:34:57PM +0200, Michael S. Tsirkin wrote: > > On Thu, Dec 17, 2015 at 03:02:12PM +0100, Peter Zijlstra wrote: > > > > > commit 9e1a27ea42691429e31f158cce6fc61bc79bb2e9 > > > > Author: Alexander Duyck <alexander.h.duyck at redhat.com> > > > > Date:

On Thu, Dec 17, 2015 at 04:09:17PM +0100, Peter Zijlstra wrote: > On Thu, Dec 17, 2015 at 04:34:57PM +0200, Michael S. Tsirkin wrote: > > On Thu, Dec 17, 2015 at 03:02:12PM +0100, Peter Zijlstra wrote: > > > > > commit 9e1a27ea42691429e31f158cce6fc61bc79bb2e9 > > > > Author: Alexander Duyck <alexander.h.duyck at redhat.com> > > > > Date:

Currently, default behavior of O_DIRECT writes was allowing concurrent writing among nodes, no cluster coherency guaranteed (no EX locks was taken), it hurts buffered reads on other nodes by reading stale data from cache. The new mount option introduce a chance to choose two different behaviors for O_DIRECT writes: * coherency=full, as the default value, will disallow concurrent O_DIRECT writes...

On Thu, Dec 17, 2015 at 03:02:12PM +0100, Peter Zijlstra wrote: > On Thu, Dec 17, 2015 at 03:26:29PM +0200, Michael S. Tsirkin wrote: > > > Note that virtio_mb() is weirdly inconsistent with virtio_[rw]mb() in > > > that they use dma_* ops for weak_barriers, while virtio_mb() uses > > > smp_mb(). > > > > It's a hack really. I think I'll clean it

On Thu, Dec 17, 2015 at 03:02:12PM +0100, Peter Zijlstra wrote: > On Thu, Dec 17, 2015 at 03:26:29PM +0200, Michael S. Tsirkin wrote: > > > Note that virtio_mb() is weirdly inconsistent with virtio_[rw]mb() in > > > that they use dma_* ops for weak_barriers, while virtio_mb() uses > > > smp_mb(). > > > > It's a hack really. I think I'll clean it

Greetings, I would like to estimate a spectral coherence between two timeseries. The stats : spectrum() returns a coh matrix which estimates coherence (squared). A basic test which from which i expect near-zero coherence: x = rnorm(500) y = rnorm(500) xts = ts(x, frequency = 10) yts = ts(y, frequency = 10) gxy = spectrum( cbind( xts, yts ) ) plot( gxy $ freq, gxy $

...t; > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > > > devices correctly. > > > > > > > OK I read up on _CCA in ACPI spec. It says: > > The _CCA object returns whether or not a bus-master device supports > > hardware managed cache coherency. Expected values are 0 to indicate it > > is not supported, and 1 to indicate that it is supported. > > > > So if host is cache coherent, and guest thinks it isn't, we incur > > unnecessary overhead by wasting coherent memory. > > I get that but you said it actual...

...t; > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > > > devices correctly. > > > > > > > OK I read up on _CCA in ACPI spec. It says: > > The _CCA object returns whether or not a bus-master device supports > > hardware managed cache coherency. Expected values are 0 to indicate it > > is not supported, and 1 to indicate that it is supported. > > > > So if host is cache coherent, and guest thinks it isn't, we incur > > unnecessary overhead by wasting coherent memory. > > I get that but you said it actual...

...o 1 will have exactly the same issue unless we start > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > devices correctly. > > Will OK I read up on _CCA in ACPI spec. It says: The _CCA object returns whether or not a bus-master device supports hardware managed cache coherency. Expected values are 0 to indicate it is not supported, and 1 to indicate that it is supported. So if host is cache coherent, and guest thinks it isn't, we incur unnecessary overhead by wasting coherent memory. I get that but you said it actually breaks - why does it? -- MST

...o 1 will have exactly the same issue unless we start > requiring firmware to advertise dma-coherent/_CCA for virtio-mmio > devices correctly. > > Will OK I read up on _CCA in ACPI spec. It says: The _CCA object returns whether or not a bus-master device supports hardware managed cache coherency. Expected values are 0 to indicate it is not supported, and 1 to indicate that it is supported. So if host is cache coherent, and guest thinks it isn't, we incur unnecessary overhead by wasting coherent memory. I get that but you said it actually breaks - why does it? -- MST