search for: coerce1

Displaying 10 results from an estimated 10 matches for "coerce1".

Did you mean: coerce
2015 Mar 25
2
[LLVMdev] Optimization puzzle...
...datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" > target triple = "x86_64-apple-macosx10.10.0" > > ; Function Attrs: nounwind readnone ssp uwtable > define { <2 x float>, float } @_Z18sampleNullOperator5PointS_(i64 %pmin.coerce0, i32 %pmin.coerce1, i64 %pmax.coerce0, i32 %pmax.coerce1) #0 { > _ZN15SamplingClosureD1Ev.exit: > %0 = icmp sgt i32 %pmin.coerce1, %pmax.coerce1 > ret { <2 x float>, float } zeroinitializer > } > > attributes #0 = { nounwind readnone ssp uwtable "less-precise-fpma...
2015 Mar 25
3
[LLVMdev] Optimization puzzle...
...6:32:64-S128" >> > target triple = "x86_64-apple-macosx10.10.0" >> > >> > ; Function Attrs: nounwind readnone ssp uwtable >> > define { <2 x float>, float } @_Z18sampleNullOperator5PointS_(i64 >> %pmin.coerce0, i32 %pmin.coerce1, i64 %pmax.coerce0, i32 %pmax.coerce1) #0 >> { >> > _ZN15SamplingClosureD1Ev.exit: >> > %0 = icmp sgt i32 %pmin.coerce1, %pmax.coerce1 >> > ret { <2 x float>, float } zeroinitializer >> > } >> > >> > attribute...
2017 May 09
3
RFC: SROA for method argument
...define signext i32 @ppc64le_func([2 x i64] %r.coerce) #0 { entry: %r = alloca %struct.record, align 8 %0 = bitcast %struct.record* %r to [2 x i64]* store [2 x i64] %r.coerce, [2 x i64]* %0, align 8 .... for x86_64 define i32 @x86_64_func(i64 %r.coerce0, i64 %r.coerce1) #0 { entry: %r = alloca %struct.record, align 8 %0 = bitcast %struct.record* %r to { i64, i64 }* %1 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %0, i32 0, i32 0 store i64 %r.coerce0, i64* %1, align 8 %2 = getelementptr inbounds { i64, i64 }, { i64, i64 }*...
2016 Dec 12
0
RFC: Adding argument allocas
...t places, or byval, or any of that > sort of stuff it has to do today. > Clang's ABI lowering is part of why I don't want to pattern match alloca+store in LLVM. Today here is how we pass 'struct P { double x, y; }' on x86_64-linux: define void @f(double %p.coerce0, double %p.coerce1) #0 { entry: %p = alloca %struct.P, align 8 %0 = bitcast %struct.P* %p to { double, double }* %1 = getelementptr inbounds { double, double }, { double, double }* %0, i32 0, i32 0 store double %p.coerce0, double* %1, align 8 %2 = getelementptr inbounds { double, double }, { double, double...
2017 Dec 06
2
[AMDGPU] Strange results with different address spaces
...], [16 x i32] addrspace(3)* @"_ZN5pacxx2v213genericKernelIZL12test_barrieriPPcE3$_0EEvT__sm0", i32 0, i32 %6 DIVERGENT: store i32 %9, i32 addrspace(3)* %10, align 4 DIVERGENT: %11 = load i32, i32 addrspace(3)* %10, align 4 DIVERGENT: %12 = getelementptr i32, i32 addrspace(1)* %callable.coerce1, i64 %idxprom.i.i.i DIVERGENT: store i32 %11, i32 addrspace(1)* %12, align 4 I’m also questioning how/where you obtained this dump. You have the declarations for the control flow intrinsics in there, which should only ever appear when the backend inserts them as part of codegen. There’s somet...
2016 Dec 10
3
RFC: Adding argument allocas
On Fri, Dec 9, 2016 at 1:30 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 12/9/2016 8:45 AM, Reid Kleckner wrote: > > On Thu, Dec 8, 2016 at 5:37 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> So IIUC basically the *only* reason for this IR change is that we don’t >> want to pattern match in debug build? >> I
2018 Apr 14
0
Creating a C-ABI compatible function signature with a struct
...C-ABI compatible function signature using LLVM? For example, this C-Code:     typedef struct vpt_data {         char x;         int a;         char c;         float b;     } vpt_data;         void vpt_test( vpt_data vd ) { Generates a function:     define void @vpt_test(i64 %vd.coerce0, i64 %vd.coerce1) #0 { And also packs/unpacks the structure values when calling/being called. If I create the function signature `vpt_test( vpt_data vd)` in LLVM however, it will just pass the structure as is to the function (push on stack I presume). This means I can't call any C functions that accep...
2013 Apr 23
0
[LLVMdev] LLVM JIT Questions
Hi Dmitri, Regarding your first question, if you can use the MCJIT engine a caching mechanism will be available very soon. I'm preparing to commit a patch today to add this capability. I'm not sure what it would take to get something similar working with the older JIT engine. I expect it would take a fair amount of work because the older JIT engine isn't designed around object
2017 Dec 05
2
[AMDGPU] Strange results with different address spaces
> On Dec 5, 2017, at 13:53, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > >> On Dec 5, 2017, at 02:51, Haidl, Michael via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi dev list, >> >> I am currently exploring the integration of AMDGPU/ROCm into the PACXX project and observing some
2013 Apr 23
3
[LLVMdev] LLVM JIT Questions
Hi all, For my current project I need a couple of informations about JIT. I seen similar questions already, but the answers are a bit older and I hope somebody can provide me a recent information. 1. In my project I frequently construct LLVM IR, compile it and execute with JIT. Because the constructed IR is often the same (but can vary depending on input data) I would like to cache produced