Displaying 6 results from an estimated 6 matches for "codegenregbank".
2019 Mar 25
2
Overlapping register groups in old 8-bit MC6809 processor.
...007fd1ddafc080 _sigtramp + 2161608032
6 libsystem_c.dylib 0x00007fff5cc411c9 abort + 127
7 libsystem_c.dylib 0x00007fff5cc09868 basename_r + 0
8 llvm-tblgen 0x000000010ba53940 (anonymous namespace)::RegisterInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream&, llvm::CodeGenRegBank const&, std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> > const&) + 2064
9 llvm-tblgen 0x000000010ba2f942 (anonymous namespace)::RegisterInfoEmitter::runTargetDesc(llvm::raw_ostream&, llvm::CodeGenTarget&, llvm::Cod...
2012 Dec 06
0
[LLVMdev] Register classes, reg unit weights calculation in tablegen
Hi,
I have a problem with the assert in Tablegen:
llvm-tblgen: /dev/shm/uabpath/dev-master/utils/TableGen/RegisterInfoEmitter.cpp:204: void <anonymous namespace>::RegisterInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed.
The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like
Cmp %1:...
2012 Dec 11
0
[LLVMdev] FW: Register classes, reg unit weights calculation in tablegen
...classes, reg unit weights calculation in tablegen
Hi,
I have a problem with the assert in Tablegen:
llvm-tblgen: /dev/shm/uabpath/dev-master/utils/TableGen/RegisterInfoEmitter.cpp:204: void <anonymous namespace>::RegisterInfoEmitter::EmitRegUnitPressure(llvm::raw_ostream &, const llvm::CodeGenRegBank &, const std::string &): Assertion `RU.Weight < 256 && "RegUnit too heavy"' failed.
The reason for this is that I have constructed pred-operands to be of the register class type FlagRegs, which holds a big union of classes, so that I can generate code like
Cmp %1:...
2012 Dec 04
0
[LLVMdev] Visual Studio 2012 cl.exe ICE while building LLVM for x64 (in TableGen) at -O2
> On Behalf Of Nicholas Chapman
>
> On 04/12/2012 06:29, Michael Spencer wrote:
> > On Mon, Dec 3, 2012 at 8:08 PM, Gordon Keiser <gkeiser at arxan.com>
> wrote:
> >> As an update to this:
> >> http://connect.microsoft.com/VisualStudio/feedback/details/769222/cl-
> >> exe-ice-when-building-llvm-trunk-at-o2
> >>
> >> Microsoft
2012 Dec 04
3
[LLVMdev] Visual Studio 2012 cl.exe ICE while building LLVM for x64 (in TableGen) at -O2
On 04/12/2012 06:29, Michael Spencer wrote:
> On Mon, Dec 3, 2012 at 8:08 PM, Gordon Keiser <gkeiser at arxan.com> wrote:
>> As an update to this:
>> http://connect.microsoft.com/VisualStudio/feedback/details/769222/cl-exe-ice-when-building-llvm-trunk-at-o2
>>
>> Microsoft has reproduced the ICE, given a workaround, and is planning a fix for a future MSVC release.
2016 Aug 23
2
How to describe the RegisterInfo?
Yes, the arch is just as you said, something like AMD GPU, but Intel GPU
don't have separate register file for 'scalar/vector'.
In fact my idea of defining the register tuples was borrowed from
SIRegisterInfo.td in AMD GPU.
But seems that AMD GPU mainly support i32/i64 register type, while Intel
GPU also support byte/short register type.
So I have to start defining the registers from