Displaying 1 result from an estimated 1 matches for "codegendesc".
2005 Oct 15
1
[LLVMdev] Dump instruction list prior register allocation
Hi there,
I have a question on the LLVM internals.
Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled
assembly) prior register allocation? Does LLVM use infinite (virtual) registers
similar to MachSUIF? This is, of course, meant for a given target in contrast
to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is
possible at this point.
Plus: