Displaying 12 results from an estimated 12 matches for "codeemitternvc0".
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codeemitternv50
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
...);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitMADSP(const Instruction *);
void emitNOT(Instruction *);
@@ -523,6 +526,25 @@ CodeEmitterNVC0::emitFMAD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMAD(const Instruction *i)
+{
+ bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
+
+ emitForm_A(i, HEX64(20000000, 00000001));
+
+ if (i->src(2).mod.neg())
+ code[0] |= 1 << 8;
+
+ roundMode_A(i);
+
+ i...
2016 Mar 16
2
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...ers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> index 6236659..ca475ce 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> @@ -281,6 +281,7 @@ CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
> {
> switch (src.getFile()) {
> case FILE_MEMORY_BUFFER:
> + case FILE_MEMORY_GLOBAL:
> srcAddr32(src, 26, 0);
> break;
> case FILE_MEMORY_LOCAL:
> @@ -1768,7 +1769,8 @@ CodeEmitterNVC0::emitCachi...
2016 Mar 16
0
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...t a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 6236659..ca475ce 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -281,6 +281,7 @@ CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
{
switch (src.getFile()) {
case FILE_MEMORY_BUFFER:
+ case FILE_MEMORY_GLOBAL:
srcAddr32(src, 26, 0);
break;
case FILE_MEMORY_LOCAL:
@@ -1768,7 +1769,8 @@ CodeEmitterNVC0::emitCachingMode(CacheMode c)
static inline bool
uses6...
2016 Mar 16
13
[PATCH mesa 1/6] tgsi_build: Fix return of uninitialized memory in tgsi_*_instruction_memory
tgsi_default_instruction_memory / tgsi_build_instruction_memory were
returning uninitialized memory for tgsi_instruction_memory.Texture and
tgsi_instruction_memory.Format. Note 0 means not set, and thus is a
correct default initializer for these.
Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory")
Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>
2016 Mar 16
2
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...gen/nv50_ir_emit_nvc0.cpp
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> index 8b9328b..6236659 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> @@ -280,7 +280,7 @@ void
> CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
> {
> switch (src.getFile()) {
> - case FILE_MEMORY_GLOBAL:
> + case FILE_MEMORY_BUFFER:
> srcAddr32(src, 26, 0);
> break;
> case FILE_MEMORY_LOCAL:
> @@ -1768,7 +1768,7 @@ CodeEmitterNVC0::emitCachingMode...
2016 Mar 16
0
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...gen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> index 6236659..ca475ce 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> @@ -281,6 +281,7 @@ CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
>> {
>> switch (src.getFile()) {
>> case FILE_MEMORY_BUFFER:
>> + case FILE_MEMORY_GLOBAL:
>> srcAddr32(src, 26, 0);
>> break;
>> case FILE_MEMORY_LOCAL:
>> @@ -1768,7 +1769...
2016 Mar 16
0
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...c/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 8b9328b..6236659 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -280,7 +280,7 @@ void
CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
{
switch (src.getFile()) {
- case FILE_MEMORY_GLOBAL:
+ case FILE_MEMORY_BUFFER:
srcAddr32(src, 26, 0);
break;
case FILE_MEMORY_LOCAL:
@@ -1768,7 +1768,7 @@ CodeEmitterNVC0::emitCachingMode(CacheMode c)
static inline bool
uses6...
2016 Mar 16
0
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> index 8b9328b..6236659 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> @@ -280,7 +280,7 @@ void
>> CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
>> {
>> switch (src.getFile()) {
>> - case FILE_MEMORY_GLOBAL:
>> + case FILE_MEMORY_BUFFER:
>> srcAddr32(src, 26, 0);
>> break;
>> case FILE_MEMORY_LOCAL:
>> @@ -1768,7 +1768,...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
...a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index d9aed34..c241973 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1406,6 +1406,8 @@ CodeEmitterNVC0::emitFlow(const Instruction *i)
} else
if (mask & 2) {
int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
+ if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
+ pcRel += 8;
// currently we don't want absolute branches...
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
...a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 1f624a5..d486c8d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2303,6 +2303,7 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
case OP_TXL:
case OP_TXD:
case OP_TXF:
+ case OP_TXG:
case OP_TXLQ:
emitTEX(insn->asTex());
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering...
2015 Nov 05
7
[PATCH mesa 0/5] nouveau: codegen: Make use of double immediates
Hi All,
This series implements using double immediates in the nouveau codegen code.
This turns the following (nvc0) code:
1: mov u32 $r2 0x00000000 (8)
2: mov u32 $r3 0x3fe00000 (8)
3: add f64 $r0d $r0d $r2d (8)
Into:
1: add f64 $r0d $r0d 0.500000 (8)
This has been tested with the 2 double shader tests which I just send to
the piglet list. On a gk208 (gk110 / SM35)
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++-------
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp