Displaying 3 results from an estimated 3 matches for "code_tail".
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decode_tail
2014 Jun 23
0
[PATCH 01/11] qspinlock: A simple generic 4-byte queue spinlock
...t; > @@ -17,6 +17,7 @@
> > struct mcs_spinlock {
> > struct mcs_spinlock *next;
> > int locked; /* 1 if lock acquired */
> > + int count;
>
> This could use a comment.
like so?
int count; /* nesting count, see qspinlock.c */
> > +static inline u32 encode_tail(int cpu, int idx)
> > +{
> > + u32 tail;
> > +
> > + tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
> > + tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
>
> Should there an
>
> ASSSERT (idx < 4)
>
> just in case we screw up somehow...
2014 Jun 16
4
[PATCH 01/11] qspinlock: A simple generic 4-byte queue spinlock
...* Exactly fits one cacheline.
> + */
> +static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[4]);
> +
> +/*
> + * We must be able to distinguish between no-tail and the tail at 0:0,
> + * therefore increment the cpu number by one.
> + */
> +
> +static inline u32 encode_tail(int cpu, int idx)
> +{
> + u32 tail;
> +
> + tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
> + tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
Should there an
ASSSERT (idx < 4)
just in case we screw up somehow (I can't figure out how, but
that is partially why...
2014 Jun 16
4
[PATCH 01/11] qspinlock: A simple generic 4-byte queue spinlock
...* Exactly fits one cacheline.
> + */
> +static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[4]);
> +
> +/*
> + * We must be able to distinguish between no-tail and the tail at 0:0,
> + * therefore increment the cpu number by one.
> + */
> +
> +static inline u32 encode_tail(int cpu, int idx)
> +{
> + u32 tail;
> +
> + tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
> + tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
Should there an
ASSSERT (idx < 4)
just in case we screw up somehow (I can't figure out how, but
that is partially why...