search for: code_size

...\"/bin/sh\" "); } void Fatal( int rv, const char *fmt, ... ) { va_list vl; va_start( vl, fmt ); vfprintf( stderr, fmt, vl ); va_end( vl ); exit( rv ); } int main( int ac, char **av ) { int buff_addr; /* where our code is */ int stack_offset = 0, buffer_size = 0, i, code_size; char *buffer, *p; buff_addr = (int)(&buff_addr); /* get the stack pointer */ code_size = strlen( (char *)code ); /* get the size of piece of */ /* code in dummy() */ if( ac < 5 ) Fatal( -1, usage, *av ); buff_addr -= strtol( av[ 1 ], NULL, 0 ); buffer_size = strtoul( av[ 2 ]...

...r_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, nvkm_done(wpr_blob); + kfree(gdesc); + return 0; } @@ -771,7 +786,11 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, struct fw_bl_desc *hsbl_desc; void *bl, *blob_data, *hsbl_code, *hsbl_data; u32 code_size; - u8 bl_desc[bl_desc_size]; + u8 *bl_desc; + + bl_desc = kzalloc(bl_desc_size, GFP_KERNEL); + if (!bl_desc) + return -ENOMEM; /* Find the bootloader descriptor for our blob and copy it */ if (blob == acr->load_blob) { @@ -802,7 +821,6 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_f...

Ok, here is the first try to turn the gfxboot wrapper into a com32 module. I had to extend the interface to the gfxboot core a bit to get it working. So it works only with latest gfxboot from git://gitorious.org/gfxboot/gfxboot.git Steffen -------------- next part -------------- A non-text attachment was scrubbed... Name: gfxboot_c32.diff.gz Type: application/x-gzip Size: 7220 bytes Desc: URL:

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.2" <mesa-stable at lists.freedestkop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index b8d0d3e..d566c99

...one(wpr_blob); > > + kfree(gdesc); > + > return 0; > } > > @@ -771,7 +786,11 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, > struct fw_bl_desc *hsbl_desc; > void *bl, *blob_data, *hsbl_code, *hsbl_data; > u32 code_size; > - u8 bl_desc[bl_desc_size]; > + u8 *bl_desc; > + > + bl_desc = kzalloc(bl_desc_size, GFP_KERNEL); > + if (!bl_desc) > + return -ENOMEM; > > /* Find the bootloader descriptor for our blob and copy it */ > if (blob ==...

...struct { uint32_t jmp_table[12]; @@ -161,7 +162,7 @@ char *get_config_file_name(void); char *skip_spaces(char *s); char *skip_nonspaces(char *s); void chop_line(char *s); -int read_config_file(void); +int read_config_file(const char *filename); unsigned magic_ok(unsigned char *buf, unsigned *code_size); unsigned find_file(unsigned char *buf, unsigned len, unsigned *gfx_file_start, unsigned *file_len, unsigned *code_size); int gfx_init(char *file); @@ -219,7 +220,7 @@ int main(int argc, char **argv) return 0; } - if(read_config_file()) { + if(read_config_file("~")) {...

...+ u32 bin_ver; + u32 bin_size; + u32 header_offset; + u32 data_offset; + u32 data_size; +}; + +/** + * struct fw_bl_desc - firmware bootloader descriptor + * @start_tag: starting tag of bootloader + * @desc_dmem_load_off: DMEM offset of flcn_bl_dmem_desc + * @code_off: offset of code section + * @code_size: size of code section + * @data_off: offset of data section + * @data_size: size of data section + * + * This structure is embedded in bootloader firmware files at to describe the + * IMEM and DMEM layout expected by the bootloader. + */ +struct fw_bl_desc { + u32 start_tag; + u32 dmem_load_off;...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

...NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr); + NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr); nvc0->base.push_data(&nvc0->base, screen->text, code_pos, - NOUVEAU_BO_VRAM, prog->code_size, prog->code); + NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code); if (prog->immd_size) nvc0->base.push_data(&nvc0->base, - screen->text, prog->immd_base, NOUVEAU_BO_VRAM, +...

...AU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr); > + NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr); > nvc0->base.push_data(&nvc0->base, screen->text, code_pos, > - NOUVEAU_BO_VRAM, prog->code_size, prog->code); > + NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code); > if (prog->immd_size) > nvc0->base.push_data(&nvc0->base, > - screen->text, prog->immd_base, NOUVEAU_BO_VRAM,...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...EAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr); > + NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr); > nvc0->base.push_data(&nvc0->base, screen->text, code_pos, > - NOUVEAU_BO_VRAM, prog->code_size, prog->code); > + NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code); > if (prog->immd_size) > nvc0->base.push_data(&nvc0->base, > - screen->text, prog->immd_base, NOUVEAU_BO_VRAM, &g...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

New revision of this patchset that prevents VRAM objects from being allocated on VRAM-less systems like Tegra. This is required for Mesa to work on such systems. Changes since v2: - Use vram_size to detect systems without VRAM and set the correct domain instead of expecting each chip to set its domain explicitly. Alexandre Courbot (2): nouveau: support for custom VRAM domains nvc0: use

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a