search for: code32

...ized or not) > - no good way to tell if a triple is normalized > - no good, centralized way to reason about which triples are allowed and valid > - the MC assembler has to link in the entire X86 backend to get subtarget info > - we don't have a good way to implement things like .code32 in the MC assembler > - LLDB replicates a lot of this code and heuristics > - we don't have good interfaces to inquire about the host > - we do std::string manipulation in llvm::Triple > - linux triples are actually quadruples! > - darwin tools that take -arch have to map th...

.../* load absolute address of pm_code in jmp_address location */ + lea (pm_code - base_address)(%rsi, 1), %rax + mov %eax, (jmp_address - base_address)(%rsi, 1) + + ljmp *(jmp_address - base_address)(%rsi, 1) + +jmp_address: + .long 0 /* address */ + .word 0x10 /* segment */ .code32 pm_code: - /* Disable IA-32e mode by clearing IA32_EFER.LME */ - xorl %eax, %eax - xorl %edx, %edx - movl $MSR_EFER, %ecx - wrmsr + /* cs segment has been updated, now update the rest */ + mov $0x18, %eax + mov %eax, %ds + mov %eax, %es + mov %eax, %fs +...

...ive instruction only if the MCE can // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table diff --git a/test/MC/X86/address-size.s b/test/MC/X86/address-size.s index b105b40..7b0bf6b 100644 --- a/test/MC/X86/address-size.s +++ b/test/MC/X86/address-size.s @@ -8,6 +8,6 @@ .code32 movb $0x0, (%si) -// CHECK: encoding: [0x67,0xc6,0x06,0x00] +// CHECK: encoding: [0x67,0xc6,0x04,0x00] movb $0x0, (%esi) // CHECK: encoding: [0xc6,0x06,0x00] -- 1.8.3.1 -- Sent with MeeGo's ActiveSync support. David Woodhouse Open Source T...

Hi All, There is recently a discussion on the LLDB list about how to deal with targets, and our current mismash of llvm::Triple and the various subclasses of TargetSubtarget leave a lot to be desired. GNU target triples are really important as input devices to the compiler (users want to specify them) but they aren't detailed enough for internal clients. Anyway, in short, I think that we

...p to update cs + + /* load absolute address of pm_code in jmp_address location */ + lea (pm_code - base_address)(%rsi, 1), %rax + mov %eax, (jmp_address - base_address)(%rsi, 1) + + ljmp *(jmp_address - base_address)(%rsi, 1) + +jmp_address: + .long 0 /* address */ + .word 0x10 /* segment */ .code32 pm_code: - /* Disable IA-32e mode by clearing IA32_EFER.LME */ - xorl %eax, %eax - xorl %edx, %edx - movl $MSR_EFER, %ecx - wrmsr + /* cs segment has been updated, now update the rest */ + mov $0x18, %eax + mov %eax, %ds + mov %eax, %es + mov %eax, %fs + mov %eax, %gs + mov %eax, %ss - /* Turn o...

...solve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, > table > diff --git a/test/MC/X86/address-size.s b/test/MC/X86/address-size.s > index b105b40..7b0bf6b 100644 > --- a/test/MC/X86/address-size.s > +++ b/test/MC/X86/address-size.s > @@ -8,6 +8,6 @@ > > .code32 > movb $0x0, (%si) > -// CHECK: encoding: [0x67,0xc6,0x06,0x00] > +// CHECK: encoding: [0x67,0xc6,0x04,0x00] > movb $0x0, (%esi) > // CHECK: encoding: [0xc6,0x06,0x00] > -- > 1.8.3.1 > > > -- > Sent with MeeGo's ActiveSy...

...%rdx, m(%rip); + +#define WRMSR(ind, m) \ + mov $ind, %ecx; \ + movq m(%rip), %rdx; \ + mov %edx, %eax; \ + shrq $0x20, %rdx; \ + wrmsr; + +#else /* !defined(__x86_64__) */ + + .code32 + +#define GREG(x) %e##x +#define SAVED_GREG(x) saved_e##x +#define DECLARE_GREG(x) saved_e##x: .long 0 +#define SAVE_GREG(x) movl GREG(x), SAVED_GREG(x) +#define LOAD_GREG(x) movl SAVED_GREG(x), GREG(x) + +#define REF(x) x + +#endif + +ENTRY(do_suspend_lowlevel) + +...

On Oct 7, 2014, at 2:26 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Dmitry, > > On 7 October 2014 10:50, Dmitry Borisenkov <d.borisenkov at samsung.com> wrote: >> fpfail.s:26: Error: invalid instruction suffix for `ret' >> >> I downloaded Intel manual and haven’t found any mention of retl instruction, > > "retl" is the

...t; - no good way to tell if a triple is normalized > > - no good, centralized way to reason about which triples are allowed and valid > > - the MC assembler has to link in the entire X86 backend to get subtarget info > > - we don't have a good way to implement things like .code32 in the MC assembler > > - LLDB replicates a lot of this code and heuristics > > - we don't have good interfaces to inquire about the host > > - we do std::string manipulation in llvm::Triple > > - linux triples are actually quadruples! > > - darwin tools that...

...q 8(%rsp), %rdi + call *(%rsp) + popq %rax + + movq 0x10(%rsp), %rax + movq 0x18(%rsp), %rcx + movq 0x20(%rsp), %rdx + movq 0x28(%rsp), %rdi + movq 0x30(%rsp), %rsi + movq 0x38(%rsp), %r8 + movq 0x40(%rsp), %r9 + movq 0x48(%rsp), %r10 + movq 0x50(%rsp), %r11 + + addl $8, (%rsp) + jmp 1b +#endif + .code32 ENTRY(no_long_mode) /* This isn't an x86-64 CPU so hang */ @@ -317,7 +374,9 @@ ENTRY(wakeup_level4_pgt) #endif #ifndef CONFIG_HOTPLUG_CPU + #ifndef CONFIG_PARAVIRT __INITDATA + #endif #endif /* * This default setting generates an ident mapping at address 0x100000 Index: clean-s...

...q 8(%rsp), %rdi + call *(%rsp) + popq %rax + + movq 0x10(%rsp), %rax + movq 0x18(%rsp), %rcx + movq 0x20(%rsp), %rdx + movq 0x28(%rsp), %rdi + movq 0x30(%rsp), %rsi + movq 0x38(%rsp), %r8 + movq 0x40(%rsp), %r9 + movq 0x48(%rsp), %r10 + movq 0x50(%rsp), %r11 + + addl $8, (%rsp) + jmp 1b +#endif + .code32 ENTRY(no_long_mode) /* This isn't an x86-64 CPU so hang */ @@ -317,7 +374,9 @@ ENTRY(wakeup_level4_pgt) #endif #ifndef CONFIG_HOTPLUG_CPU + #ifndef CONFIG_PARAVIRT __INITDATA + #endif #endif /* * This default setting generates an ident mapping at address 0x100000 Index: clean-s...

...00 00 00 02 02 00 00-00 4c 09 00 33 00 00 00 > 0a 69 6e 74 3d 30 30 30-30 30 30 30 64 20 20 65 > BTX halted The instructions that were being executed can be found, in a FreeBSD source tree, at: /usr/src/sys/boot/i386/btx/btx/btx.S Here they are for your perusal: .code32 init.8: xorl %ecx,%ecx # Zero movb $SEL_SDATA,%cl # To 32-bit movw %cx,%ss # stack /* * Launch user task. */ movb $SEL_TSS,%cl # Set task ltr %cx...

Hello, This series has been split into two patches, one for arm and one for x86. I figured that this was easier than doing it as a single combined patch, especially as the changes are functionally independent. x86 has been boot tested, but arm has not even been compile tested as I lack a suitable cross compiler. However, the changes are just text replacement, so I dont expect any issues. The

...q 8(%rsp), %rdi + call *(%rsp) + popq %rax + + movq 0x10(%rsp), %rax + movq 0x18(%rsp), %rcx + movq 0x20(%rsp), %rdx + movq 0x28(%rsp), %rdi + movq 0x30(%rsp), %rsi + movq 0x38(%rsp), %r8 + movq 0x40(%rsp), %r9 + movq 0x48(%rsp), %r10 + movq 0x50(%rsp), %r11 + + addl $8, (%rsp) + jmp 1b +#endif + .code32 ENTRY(no_long_mode) /* This isn't an x86-64 CPU so hang */ diff -urp linux-2.6.19-paravirt0/arch/x86_64/kernel/paravirt.c linux-2.6.19-paravirt1/arch/x86_64/kernel/paravirt.c --- linux-2.6.19-paravirt0/arch/x86_64/kernel/paravirt.c 2007-01-11 21:56:03.000000000 -0200 +++ linux-2.6.19-paravir...

...q 8(%rsp), %rdi + call *(%rsp) + popq %rax + + movq 0x10(%rsp), %rax + movq 0x18(%rsp), %rcx + movq 0x20(%rsp), %rdx + movq 0x28(%rsp), %rdi + movq 0x30(%rsp), %rsi + movq 0x38(%rsp), %r8 + movq 0x40(%rsp), %r9 + movq 0x48(%rsp), %r10 + movq 0x50(%rsp), %r11 + + addl $8, (%rsp) + jmp 1b +#endif + .code32 ENTRY(no_long_mode) /* This isn't an x86-64 CPU so hang */ diff -urp linux-2.6.19-paravirt0/arch/x86_64/kernel/paravirt.c linux-2.6.19-paravirt1/arch/x86_64/kernel/paravirt.c --- linux-2.6.19-paravirt0/arch/x86_64/kernel/paravirt.c 2007-01-11 21:56:03.000000000 -0200 +++ linux-2.6.19-paravir...

...ug 22 02:17:03 2003 @@ -312,8 +312,7 @@ va_list ap; int flags = BIOSCODE_FLAG | BIOSDATA_FLAG; u_int i, arg_start, arg_end; - pt_entry_t *pte; - pd_entry_t *ptd; + u_int *pte, *ptd; arg_start = 0xffffffff; arg_end = 0; @@ -372,22 +371,19 @@ args->seg.code32.base = (u_int)&bios16_jmp & PG_FRAME; args->seg.code32.limit = 0xffff; - ptd = (pd_entry_t *)rcr3(); -#ifdef PAE - ptd = (pd_entry_t *)(*ptd & PG_FRAME); -#endif + ptd = (u_int *)rcr3(); if (ptd == IdlePTD) { /* * no page table, so create one and install it...

[ This patch depends on the cross-architecture ELF cleanup patch. ] This series updates the boot protocol to 2.07 and uses it to implement paravirtual booting. This allows the bootloader to tell the kernel what kind of hardware/pseudo-hardware environment it's coming up under, and the kernel can use the appropriate boot sequence code. Specifically: - Update the boot protocol to 2.07, which

[ This patch depends on the cross-architecture ELF cleanup patch. ] This series updates the boot protocol to 2.07 and uses it to implement paravirtual booting. This allows the bootloader to tell the kernel what kind of hardware/pseudo-hardware environment it's coming up under, and the kernel can use the appropriate boot sequence code. Specifically: - Update the boot protocol to 2.07, which