search for: cmpxchg16b

...t-in function ‘malloc’ [enabled by default] malloc(mnums * mrows * mcols * mdeps * sizeof(float)); ^ himenoBMTxpa.c: In function ‘clearMat’: himenoBMTxpa.c:248:5: warning: incompatible implicit declaration of built-in function ‘free’ [enabled by default] free(Mat->m); ^ '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) Are these warnings for... '-cmpxchg16b' is not a re...

...default] > malloc(mnums * mrows * mcols * mdeps * sizeof(float)); > ^ > himenoBMTxpa.c: In function ‘clearMat’: > himenoBMTxpa.c:248:5: warning: incompatible implicit declaration of built-in function ‘free’ [enabled by default] > free(Mat->m); > ^ > '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) > '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) > '-cmpxchg16b' is not a recognized feature for this target (ignoring feature) > > Are these warnings for... > > ...

With the x86 instruction emulator no pretty complete, I''d like to re-submit this patch to support cmpxchg16b on x86-64 and at once rename the underlying emulator callback function pointer (making clear that if implemented, it is to operate on two longs rather than two 32-bit values). At the same time it fixes an apparently wrong emulator context initialization in the shadow code. Signed-off-by: Jan Beuli...

...8b 45 20 mov 0x20(%r13),%eax 22: 49 8b 7d 00 mov 0x0(%r13),%rdi 26: 48 8d 4a 08 lea 0x8(%rdx),%rcx 2a:* 49 8b 1c 04 mov (%r12,%rax,1),%rbx <-- trapping instruction 2e: 4c 89 e0 mov %r12,%rax 31: 65 48 0f c7 0f cmpxchg16b %gs:(%rdi) 36: 0f 94 c0 sete %al 39: 84 c0 test %al,%al 3b: 74 b8 je 0xfffffffffffffff5 3d: 41 rex.B 3e: 8b .byte 0x8b 3f: 45 rex.RB Code starting with the faulting instruction...

...8b 45 20 mov 0x20(%r13),%eax 22: 49 8b 7d 00 mov 0x0(%r13),%rdi 26: 48 8d 4a 08 lea 0x8(%rdx),%rcx 2a:* 49 8b 1c 04 mov (%r12,%rax,1),%rbx <-- trapping instruction 2e: 4c 89 e0 mov %r12,%rax 31: 65 48 0f c7 0f cmpxchg16b %gs:(%rdi) 36: 0f 94 c0 sete %al 39: 84 c0 test %al,%al 3b: 74 b8 je 0xfffffffffffffff5 3d: 41 rex.B 3e: 8b .byte 0x8b 3f: 45 rex.RB Code starting with the faulting instruction...

...much, so the main benefit is the tighter encoding of rdfsbase, which seems very slim. Not covered in this are tuning decisions. I think we can benefit from some variance in this area between implementations; it should not affect correctness. 32-bit support is also a separate matter. * Level A CMPXCHG16B, LAHF/SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3 This is one step above the K8 baseline and corresponds to a mainline CPU model ca. 2008 to 2011. It is also implemented by recent-ish generations of Intel Atom server CPUs (although I haven't tested the latest version). A 32-bit variant would h...

...a register, it will read it in one atomic access. For something that fits in a register and is _possible_ to write atomically, it will do so. But sometimes it's not going to be atomic. We do not for a moment try to make multi-word accesses be atomic. Not even if you could try to use some magic cmpxchg16b thing. It's not "atomic" in that sense: it will be doing multiple accesses. Similarly, if you try to write a 8- or 16-bit word on alpha with WRITE_ONCE() or you try to do other things, you have what's coming to you. And they just force some "copy to stable storage" whe...

...pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 0b15aa9541dc tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Nov 17 18:41:59 2011 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 23:09:45 2011 +0800 @@ -78,6 +78,7 @@ #define X86_FEATURE_CX16 13 /* CMPXCHG16B */ #define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */ #define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */ +#define X86_FEATURE_PCID 17 /* Process Context ID */ #define X86_FEATURE_DCA 18 /* Direct Cache Access */ #define X86_FEATURE_SSE4_1 19...

...s is a no op handler which irets immediately. It is actually in the middle of enable_nmis to reuse the iret instruction, without having a single lone aligned iret inflating the code side. And adds three new IDT entry helper routines: * _write_gate_lower This is a substitute for using cmpxchg16b to update a 128bit structure at once. It assumes that the top 64 bits are unchanged (and ASSERT()s the fact) and performs a regular write on the lower 64 bits. * _set_gate_lower This is functionally equivalent to the already present _set_gate(), except it uses _write_gate_lowe...

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests). This patch makes the host determine if the TSC is both constant and

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests). This patch makes the host determine if the TSC is both constant and

On Fri, Nov 25, 2016 at 5:17 PM, Peter Zijlstra <peterz at infradead.org> wrote: >> > What are use cases for such primitive that won't be OK with "read once >> > _and_ atomically"? >> >> I have none to hand. > > Whatever triggers the __builtin_memcpy() paths, and even the size==8 > paths on 32bit. > > You could put a WARN in there to

On Fri, Nov 25, 2016 at 5:17 PM, Peter Zijlstra <peterz at infradead.org> wrote: >> > What are use cases for such primitive that won't be OK with "read once >> > _and_ atomically"? >> >> I have none to hand. > > Whatever triggers the __builtin_memcpy() paths, and even the size==8 > paths on 32bit. > > You could put a WARN in there to

...fine X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ +#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */ #define X86_FEATURE_CID (4*32+10) /* Context ID */ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ +#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */ +#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ +#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */ +#define X86_FEATURE_S...

...ery slim. > > > > Not covered in this are tuning decisions. I think we can benefit from > > some variance in this area between implementations; it should not affect > > correctness. 32-bit support is also a separate matter. > > > > * Level A > > > > CMPXCHG16B, LAHF/SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3 > > > > This is one step above the K8 baseline and corresponds to a mainline CPU > > model ca. 2008 to 2011. It is also implemented by recent-ish > > generations of Intel Atom server CPUs (although I haven't tested the &gt...

...movl $1401, %[[R17mask:[a-z]*]] @@ -133,6 +133,6 @@ entry: ; CHECK: lock ; CHECK: cmpxchgl %{{.*}}, %gs:(%{{.*}}) - %0 = cmpxchg i32 addrspace(256)* %P, i32 0, i32 1 monotonic + %0 = cmpxchg i32 addrspace(256)* %P, i32 0, i32 1 monotonic monotonic ret void } diff --git a/test/CodeGen/X86/cmpxchg16b.ll b/test/CodeGen/X86/cmpxchg16b.ll index edbd0bc..1d5bb85 100644 --- a/test/CodeGen/X86/cmpxchg16b.ll +++ b/test/CodeGen/X86/cmpxchg16b.ll @@ -6,7 +6,7 @@ entry: ; CHECK: movl $1, %ebx ; CHECK: lock ; CHECK-NEXT: cmpxchg16b - %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst + %r = cmpxchg i128*...

..._load_tr_desc(void) +{ +} + +static void lguest_cpuid(unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + int function = *eax; + + native_cpuid(eax, ebx, ecx, edx); + switch (function) { + case 1: /* Basic feature request. */ + /* We only allow kernel to see SSE3, CMPXCHG16B and SSSE3 */ + *ecx &= 0x00002201; + /* Similarly: SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, FPU. */ + *edx &= 0x07808101; + /* Host wants to know when we flush kernel pages: set PGE. */ + *edx |= 0x00002000; + break; + case 0x80000000: + /* Futureproof this a little: if they ask how mu...

..._load_tr_desc(void) +{ +} + +static void lguest_cpuid(unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + int function = *eax; + + native_cpuid(eax, ebx, ecx, edx); + switch (function) { + case 1: /* Basic feature request. */ + /* We only allow kernel to see SSE3, CMPXCHG16B and SSSE3 */ + *ecx &= 0x00002201; + /* Similarly: SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, FPU. */ + *edx &= 0x07808101; + /* Host wants to know when we flush kernel pages: set PGE. */ + *edx |= 0x00002000; + break; + case 0x80000000: + /* Futureproof this a little: if they ask how mu...

As promised to Andrew, and with much thanks to Andi Kleen for feedback, this is the new series of lguest patches. Main change is the move to drivers/lguest (for future non-i386 expansion), but lots of cleanups driven by Andi's feedback and the documentation effort (which made me examine every line of code). It's not perfect, but it's definitely useful. Cheers, Rusty. List of

As promised to Andrew, and with much thanks to Andi Kleen for feedback, this is the new series of lguest patches. Main change is the move to drivers/lguest (for future non-i386 expansion), but lots of cleanups driven by Andi's feedback and the documentation effort (which made me examine every line of code). It's not perfect, but it's definitely useful. Cheers, Rusty. List of