search for: cmpri

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two consecutive bne instructions. I do not have a small convenient test case and there are several inline functions involved, but I hope to explain...

...VR#1025 R1 in VR#1026 entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: Live Ins: %R0 %R1 %reg1026<def,dead> = MOVr %R1<kill>, 14, %reg0, %reg0 %reg1025<def> = MOVr %R0<kill>, 14, %reg0, %reg0 %reg1024<def> = MOVr %reg1025, 14, %reg0, %reg0 CMPri %reg1025<kill>, 0, 14, %reg0, %CPSR<imp-def> Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2) bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: Predecessors according to CFG: 0x8fdac90 (#0) %...

...do you mean that my regalloc should do it? > **** Post Machine Instrs **** > # Machine code for Insert(): > Live Ins: R0 in VR#1025 R1 in VR#1026 > > entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: > Live Ins: %R0 %R1 > %LR<def> = MOVr %R0, 14, %reg0, %reg0 > CMPri %R0<kill>, 0, 14, %reg0, %CPSR<imp-def> > Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> > Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2) > > bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: > Predecessors according to CFG: 0x8fdac90 (...

...ier email about BX_RET. The issue is LR should be added to livein of BB #1. **** Post Machine Instrs **** # Machine code for Insert(): Live Ins: R0 in VR#1025 R1 in VR#1026 entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: Live Ins: %R0 %R1 %LR<def> = MOVr %R0, 14, %reg0, %reg0 CMPri %R0<kill>, 0, 14, %reg0, %CPSR<imp-def> Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2) bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: Predecessors according to CFG: 0x8fdac90 (#0) %R0&lt...

...uot;MXM", [i1], 32, (add C0, C1, C2, C3, C4, C5, C6, C7)>; // C7 = constant one and by expanding SELECT_CC to SETCC and BR_CC to BRcond. In my IntstrInfo description, I have the following patterns: //cmp (setcc) instruction def CMPri : F1<0b0000001101, (outs CondRegs:$cd), (ins GPRegs:$rn, uimm8:$uimm8), "c7 cmp\tne, $cd, $rn, $uimm8", [(set CondRegs:$cd, (setne GPRegs:$rn, uimmZExt8:$uimm8))]>; //conditional branch def BRcondrel : F3_1<0b011110, (outs), (ins CondRegs:$cd, brtarget:$offset),...

...* Post Machine Instrs **** >>> # Machine code for Insert(): >>> Live Ins: R0 in VR#1025 R1 in VR#1026 >>> >>> entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: >>> Live Ins: %R0 %R1 >>> %LR<def> = MOVr %R0, 14, %reg0, %reg0 >>> CMPri %R0<kill>, 0, 14, %reg0, %CPSR<imp-def> >>> Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> >>> Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2) >>> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predec...

...o. > > >> **** Post Machine Instrs **** >> # Machine code for Insert(): >> Live Ins: R0 in VR#1025 R1 in VR#1026 >> >> entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0: >> Live Ins: %R0 %R1 >> %LR<def> = MOVr %R0, 14, %reg0, %reg0 >> CMPri %R0<kill>, 0, 14, %reg0, %CPSR<imp-def> >> Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill> >> Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2) >> >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to...

...ion [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc,...

...ump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:g...

...ump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:g...

...ion [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc,...

...ll>, 12 %I1<def> = ADDri %I1<kill>, <ga:@stat>[TF=5] %I3<def> = SETHIi <ga:@lstat>[TF=3] %I3<def> = ADDri %I3<kill>, <ga:@lstat>[TF=4] %I3<def> = SLLXri %I3<kill>, 12 %I3<def> = ADDri %I3<kill>, <ga:@lstat>[TF=5] CMPri %I2<kill>, 0, %ICC<imp-def> %I1<def,tied2> = MOVXCCrr %I3<kill>, %I1<kill,tied0>, 9, %ICC<imp-use,kill> JMPLrr %I1<kill>, %G0, %O0<kill>, %O1<undef>, %O0<imp-def,dead>, %O1<imp-def,dead>, %ICC<imp-def,dead>, %O6<imp-use&gt...

On Wed, Jun 26, 2013 at 3:59 PM, Nadav Rotem <nrotem at apple.com> wrote: > > On Jun 26, 2013, at 3:51 PM, Chandler Carruth <chandlerc at google.com> wrote: > > Can you suggest an alternative solution? Can you describe why you don't > think metadata is the right container? This alone isn't really helpful at > moving us toward something that there has been