Displaying 9 results from an estimated 9 matches for "cmpne".
2012 Feb 02
0
[LLVMdev] How to improve code generated for 'getelementptr' ?
...;; @Init1
;; BB#0: ;; %entry
ldi R1 , 0
ldi R2 , 1
ldi R3 , 100
_BB1_1: ;; %for.body
;; =>This Inner Loop Header: Depth=1
mov R4 , R1
add R1 , 1
mov R5 , R0
sll R4 , 2
cmpne R1 , R3
add R5 , R4
bcc24 _BB1_1
sw R2 , R5, 0
;; BB#2: ;; %for.end
b r15
nop
.globl _Init2
_Init2: ;; @Init2
;; BB#0: ;; %entry
cmpeq R0 , R1
bcc24 _BB2_3
nop
;; BB#1:
ldi R2 , 4
_BB2...
2012 Jul 25
2
[LLVMdev] Question about an unusual jump instruction
...ter code selection I've something like:
BB0:
%vreg0<def> = COPY %R0; // R0 contains 'a'
J <#BB1>
BB1:
%vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3>
J <#BB2>
BB2:
// loop body
BB3:
%vreg3<def> = ADDI %vreg1<kill>, 1
CMPNE %vreg3, 0, %SR<implicit,def>
JNZ <#BB1>
J <#BB4>
BB4:
// end
With the optimization pass I replace the decrement, comparison and conditional
jump with the DECJNZ. The resulting code will be:
BB0:
%vreg0<def> = COPY %R0; // R0 contains 'a'
J <#BB1&...
2012 Jul 25
0
[LLVMdev] Question about an unusual jump instruction
...> %vreg0<def> = COPY %R0; // R0 contains 'a'
> J <#BB1>
> BB1:
> %vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3>
> J <#BB2>
> BB2:
> // loop body
> BB3:
> %vreg3<def> = ADDI %vreg1<kill>, 1
> CMPNE %vreg3, 0, %SR<implicit,def>
> JNZ <#BB1>
> J <#BB4>
> BB4:
> // end
>
> With the optimization pass I replace the decrement, comparison and conditional
> jump with the DECJNZ. The resulting code will be:
>
> BB0:
> %vreg0<def> = COPY...
2015 Aug 10
2
ARM: Predicated returns considered analyzable?
Hello,
The function ARMBaseInstrInfo::AnalyzeBranch contains the following
piece of code:
} else if (I->isReturn()) {
// Returns can't be analyzed, but we should run cleanup.
CantAnalyze = !isPredicated(I);
} else {
This could lead to cases where for a block that ends with a
conditional return, AnalyzeBranch returns false (i.e. analyzed),
both TBB and FBB are
2015 Aug 12
2
ARM: Predicated returns considered analyzable?
...terminator tBLXi. This looks wrong. Does anyone have any
comments on
> this?
Isn't it because one of the predicates is CPSR, which means it's a
conditional instruction, so not really a terminator?
This lowers to the expected:
str lr, [sp, #-4]!
cmp r1, #0
it ne
cmpne r0, #3
bhi .LBB0_2 <-- Turned into a conditional jump
bl bar
.LBB0_2:
ldr lr, [sp], #4
bx lr
cheers,
--renato
----- Me:
On 8/11/2015 8:32 AM, Renato Golin wrote:
> On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev
> <llvm-dev at lists.llvm.org>...
2012 Jul 25
1
[LLVMdev] Question about an unusual jump instruction
...0 contains 'a'
>> J <#BB1>
>> BB1:
>> %vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3>
>> J <#BB2>
>> BB2:
>> // loop body
>> BB3:
>> %vreg3<def> = ADDI %vreg1<kill>, 1
>> CMPNE %vreg3, 0, %SR<implicit,def>
>> JNZ <#BB1>
>> J <#BB4>
>> BB4:
>> // end
>>
>> With the optimization pass I replace the decrement, comparison and conditional
>> jump with the DECJNZ. The resulting code will be:
>>
>>...
2012 Jul 30
0
[LLVMdev] IR optimization pass ideas for backend porting before ISel
...> *(arr+j+1)) {
int t = *(arr+j);
*(arr+j) = *(arr+j+1);
*(arr+j+1) = t;
}
}
Part of assemble codes (bubbleSort-gcc-O2.s) from GCC M*Core backend with
-O2:
.L3:
cmplti r3,1
jbt .L6
mov r7,r2
movi r6,0
.L5:
ldw r5,(r7)
ldw r4,(r7,4)
...
.L4:
addi r6,1
addi r7,4
cmpne r3,r6
jbt .L5
The address calculating formula for such code is
N(0) = arr;
N(n) = N(n-1) + ElementSize, n>= 1
which r2 stands for arr, r7 stands for the next address, and ElementSize
of int type is 4.
However, LLVM GEP adopts a rule as N(n) = arr + n * ElementSize, and may
produce several...
2012 Jan 09
39
[PATCH v4 00/25] xen: ARMv7 with virtualization extensions
Hello everyone,
this is the fourth version of the patch series that introduces ARMv7
with virtualization extensions support in Xen.
The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile
Express simulator.
See the following announce email for more informations about what we
are trying to achieve, as well as the original git history:
See
2011 Dec 06
57
[PATCH RFC 00/25] xen: ARMv7 with virtualization extensions
Hello everyone,
this is the very first version of the patch series that introduces ARMv7
with virtualization extensions support in Xen.
The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile
Express simulator.
See the following announce email for more informations about what we
are trying to achieve, as well as the original git history:
See