Displaying 5 results from an estimated 5 matches for "cmpicc".
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mpicc
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...ofile with zero results,
//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//define the instruction
def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
"cmp $src1 $src2;",
[(MYcmpicc IntRegs:$src1, IntRegs:$src2)]>...
2008 Sep 19
0
[LLVMdev] Custom Opcodes versus built-in opcodes
...e(Opc, MVT::Other, Chain, Dest,
> DAG.getConstant(SPCC, MVT::i32), CompareFlag);
Actually, I'm wrong, sorry about that. It looks like the encoding is
in the definition of the enum:
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
CMPICC, // Compare two GPR operands, set icc.
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
BRFCC, // Branch to dest on fcc condition
...
Are your "targetISD" enums properly defined with the offset?
getTargetN...
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
...onAction(ISD::ADDC, MVT::i64, Custom);
setOperationAction(ISD::ADDE, MVT::i64, Custom);
***************
*** 1808,1835 ****
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((SPISD::NodeType)Opcode) {
! case SPISD::FIRST_NUMBER: break;
! case SPISD::CMPICC: return "SPISD::CMPICC";
! case SPISD::CMPFCC: return "SPISD::CMPFCC";
! case SPISD::BRICC: return "SPISD::BRICC";
! case SPISD::BRXCC: return "SPISD::BRXCC";
! case SPISD::BRFCC: return "SPISD::BRFCC";
! case SPISD:...
2008 Sep 19
2
[LLVMdev] Custom Opcodes versus built-in opcodes
________________________________
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent: Friday, September 19, 2008 10:49 AM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes
On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote:
I am using lowering instructions and using custom opcodes that
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...ts which are of the same type (int)
> def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
> SDTCisSameAs<0, 1>, SDTCisInt<0>
> ]>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp,
> [SDNPOutFlag]>;
>
>
> //define the instruction
> def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
> "cmp $src1 $src2;",
> [(MYcmpicc...