Displaying 20 results from an estimated 24 matches for "cmpeqri".
2012 Aug 09
0
[LLVMdev] MI bundle liveness attributes
...ore contents - currently we expose internal def/use/kill information to a
bundle header - something like this:
BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>
* %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0;
* %P0<def> = CMPEQri %R16, 0;
Here CMPEQri is a compare to a predicate register instruction, and
LDriuh_cdnNotPt is a _conditional_ load, which might or might not
Take place based on the outcome of the compare... As such R0 might or might
not be defined in this bundle, which obviously changes the liveness update
pro...
2012 Aug 09
2
[LLVMdev] MI bundle liveness attributes
...ion.
The Bundle would be:
BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>,
%R0<imp-use,kill>
* %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0,
%R0<imp-use,kill>
* %P0<def> = CMPEQri %R16, 0
The individual instruction would be:
%R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0, %R0<imp-use,
kill>;
How would you use cond-def/uses? How would they change liveness?
Best,
Arnold
--
Qualcomm I...
2012 Aug 10
2
[LLVMdev] MI bundle liveness attributes
...expose internal def/use/kill information to a
> bundle header - something like this:
>
>
> BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>
> * %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0;
> * %P0<def> = CMPEQri %R16, 0;
>
> Here CMPEQri is a compare to a predicate register instruction, and
> LDriuh_cdnNotPt is a _conditional_ load, which might or might not
> Take place based on the outcome of the compare... As such R0 might or might
> not be defined in this bundle, which obviously changes...
2012 Aug 13
0
[LLVMdev] MI bundle liveness attributes
...information
> > to a bundle header - something like this:
> >
> >
> > BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>
> > * %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0;
> > * %P0<def> = CMPEQri %R16, 0;
> >
> > Here CMPEQri is a compare to a predicate register instruction, and
> > LDriuh_cdnNotPt is a _conditional_ load, which might or might not
> Take
> > place based on the outcome of the compare... As such R0 might or
> might
> > not be defined in th...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
> %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
> %vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
> JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> JMP <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> BB#2: derived from LLVM BB %for.end
> Predecessors according to CFG: BB#1
&g...
2012 May 11
6
[LLVMdev] Scheduler Roadmap
Dave,
Thank you for your interest. Please see my replies below. Sorry that my
terminology is not as crisp as Andy's, but I think you can see what I mean.
Sergei
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
> -----Original Message-----
> From: dag at cray.com [mailto:dag at cray.com]
> Sent: Friday, May 11, 2012 12:14 PM
> To: Sergei Larin
> Cc:
2012 Aug 09
0
[LLVMdev] MI bundle liveness attributes
...;
> BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>,
> %R0<imp-use,kill>
> * %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0,
> %R0<imp-use,kill>
> * %P0<def> = CMPEQri %R16, 0
>
> The individual instruction would be:
>
> %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0, %R0<imp-use,
> kill>;
>
> How would you use cond-def/uses? How would they change live...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<<
First use uninitialized vreg10
%vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
%vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
%vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
JMP <BB#2>
Successors according to CFG: BB#2 BB#1
BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
%vreg7<def> =...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...reg1,%vreg10 <<<<<<<<<<<<< First use uninitialized vreg10
> %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9
> %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> JMP <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> BB#2: derived from LLVM BB %for.end
> Predecessors according to CFG: BB#1...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...eg4,%vreg3
%vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>;
IntRegs:%vreg1,%vreg5,%vreg2
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
%vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg3,%vreg2
%vreg6<def> = CMPEQri %vreg2, 0; PredRegs:%vreg6 IntRegs:%vreg2
JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
JMP <BB#2>
Successors according to CFG: BB#2 BB#1
BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
%vreg7<def> = L...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> So if this early exit is taken:
>
> // SSA defs do not have output/anti dependencies.
> // The current operand is a def, so we have at least one.
> if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
> return;
>
> we do not ever get to this point:
>
>
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...ding to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
192B JMP <BB#2>
Successors according to CFG: BB#2 BB#1
208B BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
224B...
2013 Feb 04
2
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
...the
bundle header).
v BUNDLE %P3<imp-def>, %R29<imp-use>, %D8<imp-use,kill>,
%D9<imp-use,kill>, %R6<imp-use>
*^v STrid_indexed %R29, 80, %D8<kill>; mem:ST8[FixedStack2]
*^v STrid_indexed %R29, 72, %D9<kill>; mem:ST8[FixedStack3]
*^v %P3<def> = CMPEQri %R6, 0
*^ %R17<def> = TFR_cdnNotPt %P3<internal>, %R1
v BUNDLE %R29<imp-use>, %D10<imp-use,kill>, %R7<imp-use>, %D6<imp-use>
(next bundle).
finalizeBundle() is called with:
FirstMI == STrid_indexed %R29, 80, %D8<kill>; mem:ST8[FixedStack2]
LastMI ==...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...t; 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> 192B JMP <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> 208B BB#2: derived from LLVM BB %for.end
> Predecessors ac...
2013 Feb 04
0
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
...t; v BUNDLE %P3<imp-def>, %R29<imp-use>, %D8<imp-use,kill>,
> %D9<imp-use,kill>, %R6<imp-use>
> *^v STrid_indexed %R29, 80, %D8<kill>; mem:ST8[FixedStack2]
> *^v STrid_indexed %R29, 72, %D9<kill>; mem:ST8[FixedStack3]
> *^v %P3<def> = CMPEQri %R6, 0
> *^ %R17<def> = TFR_cdnNotPt %P3<internal>, %R1
> v BUNDLE %R29<imp-use>, %D10<imp-use,kill>, %R7<imp-use>, %D6<imp-use>
> (next bundle).
>
> finalizeBundle() is called with:
>
> FirstMI == STrid_indexed %R29, 80, %D8<kill>...
2012 Aug 15
3
[LLVMdev] MI bundle liveness attributes
...gt;> to a bundle header - something like this:
>>>
>>>
>>> BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>, %R16<imp-use>
>>> * %R0<def> = LDriuh_cdnNotPt %P0<kill,internal>, %R16, 0;
>>> * %P0<def> = CMPEQri %R16, 0;
>>>
>>> Here CMPEQri is a compare to a predicate register instruction, and
>>> LDriuh_cdnNotPt is a _conditional_ load, which might or might not
>> Take
>>> place based on the outcome of the compare... As such R0 might or
>> might
>>&g...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2013 Feb 02
0
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
On Feb 1, 2013, at 3:43 PM, "Sergei Larin" <slarin at codeaurora.org> wrote:
> I have a question about the following (four) asserts recently added in
> bundleWithPred() and bundleWithSucc() (see below). What is the real danger
> of reasserting a connection even if it already exist?
The intention was to identify code that may have been converted from the old style a
2013 Feb 04
2
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
...DLE %P3<imp-def>, %R29<imp-use>, %D8<imp-use,kill>,
> > %D9<imp-use,kill>, %R6<imp-use> *^v STrid_indexed %R29, 80,
> > %D8<kill>; mem:ST8[FixedStack2] *^v STrid_indexed %R29, 72,
> > %D9<kill>; mem:ST8[FixedStack3] *^v %P3<def> = CMPEQri %R6, 0
> > *^ %R17<def> = TFR_cdnNotPt %P3<internal>, %R1
> > v BUNDLE %R29<imp-use>, %D10<imp-use,kill>, %R7<imp-use>,
> > %D6<imp-use> (next bundle).
> >
> > finalizeBundle() is called with:
> >
> > FirstMI == STrid...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...;def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> > 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> > IntRegs:%vreg10,%vreg9
> > 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> > 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6
> IntRegs:%vreg10
> > 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> > 192B JMP <BB#2>
> > Successors according to CFG: BB#2 BB#1
> >
> > 208B BB#2: derived from LLVM BB %for.en...