search for: cmpeq

...have a simple testcase that shows the problem? > >-Chris Hi Chris, I am targeting the alpha platform. I pasted a portion of the problem code below. I starred a select in the join block that is fed by the seteq (%tmp.37) in the entry block. The resultant alpha code places an unnecessary cmpeq in block 'entry'. When I move the definition of %tmp.37 to block 'join', the Alpha backend correctly eliminates the cmpeq. I think rather than changing the cast/seteq behavior, I can get the same results for alpha by moving the seteq to the block where it is used. -Eric implemen...

...e problems for architectures that use conditional moves to implement select (alpha and ARM). For example, on 2006/09/03 a "if (a) return 0; else return 1;" compiled to ---------------------------------------- zapnot $17,15,$1 zapnot $16,15,$2 bis $31,$31,$0 cmpeq $2,$1,$1 cmoveq $1,1,$0 ret $31,($26),1 ---------------------------------------- Now it compiles to ---------------------------------- zapnot $17,15,$0 zapnot $16,15,$1 cmpeq $1,$0,$0 beq $0,$BB1_2 #return $BB1_1: #cond_true bis $31,$31,$0...

...ckend on which I have been working, we have a compare instruction that sets a flag (true or false), and a conditional branch instruction, that jumps if the flag is true. Initially, I tried to specify this by providing a lowering of the compare instruction : (CCReg only contains one register) def CMPEQ : Instr< (outs CCReg:$dst), (ins IntRegs:$lhs, IntRegs:$rhs), "cmpeq $lhs, $src", [(cmpeq IntRegs:$dst, IntRegs:$src)>; def BCC : Instr< (outs), (ins CCReg:$cc, brtarget:$addr), "bcc $addr", [(brcond CCReg:$cc, bb:$addr)] >; This worked, but for m...

...how it handles select. For example: int %foo(int %x) { %b = seteq int %x, 5 %r = select bool %b, int 3, int 7 ret int %r } int %bar(int %x) { %b = seteq int %x, 5 br bool %b, label %t, label %f t: ret int 1 f: ret int 2 } compiles to: foo: lda $0,3($31) zapnot $16,15,$1 cmpeq $1,5,$1 cmoveq $1,7,$0 ret $31,($26),1 bar: zapnot $16,15,$0 cmpeq $0,5,$0 beq $0,$BB2_2 #f $BB2_1: #t lda $0,1($31) ret $31,($26),1 $BB2_2: #f lda $0,2($31) ret $31,($26),1 Which is not a problem with the instruction select...

On Jan 20, 2012, at 6:40 AM, Jonas Paulsson wrote: > > What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? > > Yes, I can move a CR to a GPR and save it to the stack, but due to a very irregular register file this is about 10 times more expensive than saving/restoring an ordinary register. These registers should basically never > have to

> On Jan 19, 2012, at 5:31 AM, Jonas Paulsson wrote: > LLVM would have to be extended with an RegClass/register-attribute 'spillable' > > > What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? Yes, I can move a CR to a GPR and save it to the stack, but due to a very irregular register file this is about 10 times more expensive

Hi, I'm trying to emit a conditional move in the ARM backend for a custom intrinsic. Basically, I want to emit the following the following instruction sequence: cmp r0, r1 moveq r2, #1 To implement this, I first emit a compare instruction and then I'm trying to emit the conditional move, which is failing. BuildMI(&MBB, DL, TII->get(ARM::CMPrr))

...mov R4 , R1 add R1 , 1 mov R5 , R0 sll R4 , 2 cmpne R1 , R3 add R5 , R4 bcc24 _BB1_1 sw R2 , R5, 0 ;; BB#2: ;; %for.end b r15 nop .globl _Init2 _Init2: ;; @Init2 ;; BB#0: ;; %entry cmpeq R0 , R1 bcc24 _BB2_3 nop ;; BB#1: ldi R2 , 4 _BB2_2: ;; %while.body ;; =>This Inner Loop Header: Depth=1 sw R2 , R0, 0 add R0 , 4 cmpne R1 , R0 bcc24 _BB2_2 nop _BB2_3: ;; %wh...

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See