Displaying 4 results from an estimated 4 matches for "cmp32mr".
2011 Jan 16
1
[LLVMdev] About register allocation
...MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b]
MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d]
MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x]
%reg16384<def> = MOV32rm <fi#3>, 1, %reg0, 0, %reg0; mem:LD4[%b]
GR32:%reg16384
CMP32mr <fi#2>, 1, %reg0, 0, %reg0, %reg16384<kill>,
%EFLAGS<imp-def>; mem:LD4[%a] GR32:%reg16384
JLE_4 <BB#2>, %EFLAGS<imp-use,kill>
The machine code after register allocation:
MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a]
MOV32mi <fi#...
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...B<kill>, %ECX<imp-use,kill>, %ECX<imp-def>;
> dbg:FastBoard.cpp:1938:38
>
> .
>
> .
>
> .
>
> CMP32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>;
> mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26
>
> The relevant portion of the RDF graph that is constructed is shown below:
>
> BB#0:
>
> s3: MOV32r0 [d4<ECX>(,d50,u245):, d5<EFLAGS>!(,d...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...gt;> dbg:FastBoard.cpp:1938:38
>>>
>>> .
>>>
>>> .
>>>
>>> .
>>>
>>> CMP32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>;
>>> mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26
>>>
>>> The relevant portion of the RDF graph that is constructed is shown below:
>>>
>>> BB#0:
>>>
>>> s3: MOV3...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof,
Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts.
Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a